1/17
March 2000
M48Z512A
M48Z512AY
4 Mbit (512Kb x8) ZEROPOWER
SRAM
s
INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
s
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s
10 YEARS of DATA RETENTION in the
ABSENCE of POWER
s
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
M48Z512A: 4.50V
V
PFD
4.75V
M48Z512AY: 4.20V
V
PFD
4.50V
s
BATTERY INTERNALLY ISOLATED UNTIL
POWER IS APPLIED
s
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 512K x 8 SRAMs
s
SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 28-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
s
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY
s
SNAPHAT
HOUSING (BATTERY) IS
REPLACEABLE
Figure 1. Logic Diagram
AI02043
19
A0-A18
W
DQ0-DQ7
VCC
M48Z512A
M48Z512AY
G
VSS
8
E
Table 1. Signal Names
A0-A18
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
32
1
32
1
SOH28
Surface Mount Chip Set Solution (CS)
SNAPHAT (SH)
Battery
PMDIP32 (PM)
Module
TSOP II 32
(10 x 20mm)
M48Z512A, M48Z512AY
2/17
Figure 2. DIP Connections
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
A13
A10
A8
A9
DQ7
A15
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A16
A18
VCC
AI02044
M48Z512A
M48Z512AY
10
1
2
5
6
7
8
9
11
12
13
14
15
16
30
29
26
25
24
23
22
21
20
19
18
17
A12
A14
W
A17
3
4
28
27
32
31
Table 2. Absolute Maximum Ratings
(1)
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260
C for 10 seconds (total thermal budget not to exceed 150
C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Note: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
C
T
STG
Storage Temperature (V
CC
Off)
40 to 70
C
T
BIAS
Temperature Under Bias
40 to 70
C
T
SLD
(2)
Lead Solder Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to 7
V
V
CC
Supply Voltage
0.3 to 7
V
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
High Z
Battery Back-up Mode
DESCRIPTION
The M48Z512A/512AY ZEROPOWER
RAM is a
non-volatile 4,194,304 bit Static RAM organized
as 524,288 words by 8 bits. The device combines
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic 32 pin DIP Module.
For surface mount environments ST provides a
Chip Set solution consisting of a 28 pin 330mil
SOIC NVRAM Supervisor (M40Z300) and a 32 pin
TSOP Type II (10 x 20mm) LPSRAM (M68Z512)
packages.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is "M4Zxx-BR00SH1".
3/17
M48Z512A, M48Z512AY
The M48Z512A/512AY also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single 5V supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
CC
. As V
CC
falls
below approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
The ZEROPOWER RAM replaces industry stan-
dard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special write
Figure 3. Block Diagram
AI02045
INTERNAL
BATTERY
E
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
512K x 8
SRAM ARRAY
A0-A18
DQ0-DQ7
W
G
POWER
E
timing or limitations on the number of writes that
can be performed.
The M48Z512A/512AY has its own Power-fail De-
tect Circuit. The control circuitry constantly moni-
tors the single 5V supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operations brought on by low V
CC
. As V
CC
falls below approximately 3V, the control circuitry
connects the battery which sustains data until valid
power returns.
M48Z512A, M48Z512AY
4/17
Figure 4. Hardware Hookup for SMT Chip Set
(1)
Note: 1. For pin connections, see individual data sheets for M40Z300 and M68Z512 at www.st.com.
2. Connect THS pin to V
OUT
if 4.2V
V
PFD
4.5V (M48Z512AY) or connect THS pin to V
SS
if 4.5V
V
PFD
4.75V (M48Z512A).
3. SNAPHAT top ordered separately.
AI03631
E1CON
VSS
VOUT
THS
(2)
A
M40Z300
E
B
E2CON
E3CON
E4CON
VSS
E2
VCC
M68Z512
E
A0-A18
W
DQ0-DQ7
SNAPHAT
BATTERY
(3)
RST
BL
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Figure 5. AC Testing Load Circuit
AI01030
5V
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
1.9k
DEVICE
UNDER
TEST
1k
5/17
M48Z512A, M48Z512AY
Table 5. Capacitance
(1, 2)
(T
A
= 25
C, f = 1MHz)
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T
A
= 0 to 70
C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Note: 1. Outputs deselected.
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70
C)
Note: 1. All voltages referenced to V
SS
.
2. At 25
C.
Symbol
Parameter
Test Condit ion
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
10
pF
C
IO
(3)
Input / Output Capacitance
V
OUT
= 0V
10
pF
Symbol
Parameter
Test Conditio n
Min
Max
Unit
I
LI
(1)
Input Leakage Current
0V
V
IN
V
CC
1
A
I
LO
(1)
Output Leakage Current
0V
V
OUT
V
CC
1
A
I
CC
Supply Current
E = V
IL
, Outputs open
115
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
10
mA
I
CC2
Supply Current (Standby) CMOS
E
V
CC
0.2V
5
mA
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.4
V
Symbol
Parameter
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage
M48Z512A
4.5
4.6
4.75
V
M48Z512AY
4.2
4.3
4.5
V
V
SO
Battery Back-up Switchover Voltage
3
V
t
DR
(2)
Data Retention Time
10
YEARS
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