1/21
October 2003
Rev. 2.4
M48Z512A
M48Z512AY, M48Z512AV*
4 Mbit (512 Kbit x 8) ZEROPOWER
SRAM
* Contact Local Sales Office
FEATURES SUMMARY
s
INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, and
BATTERY
s
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s
10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
s
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s
TWO WRITE PROTECT VOLTAGES:
(V
PFD
= Power-fail Deselect Voltage)
M48Z512A: V
CC
= 4.75 to 5.5V
4.5V
V
PFD
4.75V
M48Z512AY: V
CC
= 4.5 to 5.5V
4.2V
V
PFD
4.5V
M48Z512AV: V
CC
= 3.0 to 3.6V
2.8V
V
PFD
3.0V
s
BATTERY INTERNALLY ISOLATED UNTIL
POWER IS APPLIED
s
PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 512K x 8 SRAMs
s
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP WHICH
CONTAINS THE BATTERY
s
SNAPHAT HOUSING (BATTERY) IS
REPLACEABLE
s
EQUIVALENT SURFACE-MOUNT (SMT)
SOLUTION REQUIRES A 28-PIN M40Z300/W
and A STAND-ALONE 128K x8 LPSRAM
(SNAPHAT
Top to be ordered separately)
Figure 1. 32-pin PMDIP Module
PMDIP32 (PM)
Module
32
1
M48Z512A, M48Z512AY, M48Z512AV*
2/21
TABLE OF CONTENTS
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DIP Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Hardware Hookup for Equivalent Surface-Mount (SMT) Solution (Figure 5.) . . . . . . . . . . . . . . . . . . 5
Equivalent Surface-Mount (SMT) Solution (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating and AC Measurement Conditions (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC Measurement Load Circuit (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Capacitance (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating Modes (Table 7.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable or Output Enable Controlled, READ Mode AC Waveforms (Figure 7.). . . . . . . . . . . . . 9
Address Controlled, READ Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
READ Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE Enable Controlled, WRITE AC Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Enable Controlled, WRITE AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE Mode AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Down/Up Mode AC Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Down/Up AC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Down/Up Trip Points DC Characteristics (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Supply Voltage Protection (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SNAPHAT Battery Table (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/21
M48Z512A, M48Z512AY, M48Z512AV*
DESCRIPTION
The M48Z512A/Y/V ZEROPOWER
RAM is a
non-volatile, 4,194,304-bit Static RAM organized
as 524,288 words by 8 bits. The device combines
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic, 32-pin DIP Module.
For surface-mount environments ST provides an
equivalent SMT solution consisting of a 28-pin,
330mil SOIC NVRAM SUPERVISOR (M40Z300/
W) and a 32-pin, (Type II TSOP, 10 x 20mm) 4Mb
LPSRAM. Both 5V and 3V versions are available
(see Table 2, page 5).
The unique design allows the SNAPHAT
battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface-mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is "M4Z32-BR00SH1."
Figure 2. Logic Diagram
Table 1. Signal Names
AI02043
19
A0-A18
W
DQ0-DQ7
VCC
M48Z512A
M48Z512AY
M48Z512AV
G
VSS
8
E
A0-A18
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable Input
G
Output Enable Input
W
WRITE Enable Input
V
CC
Supply Voltage
V
SS
Ground
PDF 
ZIP
