M48Z58
M48Z58Y
64 Kbit (8Kb x 8) ZEROPOWER
SRAM
March 1999
1/17
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
M48Z58: 4.50V
V
PFD
4.75V
M48Z58Y: 4.20V
V
PFD
4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT
TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs
DESCRIPTION
The M48Z58/58Y ZEROPOWER
RAM is an 8K x
8 non-volatile static RAM that integrates power-fail
deselect circuitry and battery control logic on a
single die. The monolithic chip is available in two
special packages to provide a highly integrated
battery backed-up memory solution.
AI01176B
13
A0-A12
W
DQ0-DQ7
VCC
M48Z58
M48Z58Y
G
VSS
8
E
Figure 1. Logic Diagram
A0-A12
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
28
1
PCDIP28 (PC)
Battery CAPHAT
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
Grade 1
Grade 6
0 to 70
40 to 85
C
T
STG
Storage Temperature (V
CC
Off)
40 to 85
C
T
SLD
(2)
Lead Solder Temperature for 10 seconds
260
C
V
IO
Input or Output Voltages
0.3 to 7
V
V
CC
Supply Voltage
0.3 to 7
V
I
O
Output Current
20
mA
P
D
Power Dissipation
1
W
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260
C for 10 seconds (total thermal budget not to exceed 150
C for longer than 30 seconds).
CAUTION: Negative undershoots below 0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 2. Absolute Maximum Ratings
(1)
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
(2)
X
X
X
High Z
CMOS Standby
Deselect
V
SO
X
X
X
High Z
Battery Back-up Mode
Notes: 1. X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
2. See Table 7 for details.
Table 3. Operating Modes
(1)
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
NC
A10
A8
A9
DQ7
W
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
NC
VCC
AI01177B
M48Z58
M48Z58Y
8
1
2
3
4
5
6
7
9
10
11
12
13
14
16
15
28
27
26
25
24
23
22
21
20
19
18
17
Figure 2A. DIP Pin Connections
AI01178B
8
2
3
4
5
6
7
9
10
11
12
13
14
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
NC
A10
A8
A9
DQ7
W
A11
G
E
DQ5
DQ1
DQ2
DQ3
VSS
DQ4
DQ6
A12
NC
VCC
M48Z58Y
Figure 2B. SOIC Pin Connections
Warning: NC = Not Connected.
Warning: NC = Not Connected.
2/17
M48Z58, M48Z58Y
AI01030
5V
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
1.9k
DEVICE
UNDER
TEST
1k
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI01394
LITHIUM
CELL
VPFD
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8K x 8
SRAM ARRAY
A0-A12
DQ0-DQ7
E
W
G
POWER
Figure 3. Block Diagram
The M48Z58/58Y is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The 28 pin 600mil DIP CAPHAT
TM
houses the
M48Z58/58Y silicon with a long life lithium button
cell in a single package.
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery. The unique design allows the SNAPHAT
battery package to be mounted on top of the SOIC
package after the completion of the surface mount
process. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to the
high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SOIC and battery packages are shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form.
DESCRIPTION (cont'd)
3/17
M48Z58, M48Z58Y
Symbol
Parameter
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
V
IN
V
CC
1
A
I
LO
Output Leakage Current
0V
V
OUT
V
CC
5
A
I
CC
Supply Current
Outputs open
50
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
3
mA
I
CC2
Supply Current (Standby) CMOS
E = V
CC
0.2V
3
mA
V
IL
Input Low Voltage
0.3
0.8
V
V
IH
Input High Voltage
2.2
V
CC
+ 0.3
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage
I
OH
= 1mA
2.4
V
Table 6. DC Characteristics
(T
A
= 0 to 70
C or 40 to 85
C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
10
pF
C
IO
(3)
Input / Output Capacitance
V
OUT
= 0V
10
pF
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 5. Capacitance
(1, 2)
(T
A
= 25
C)
Symbol
Parameter
Min
Typ
Max
Unit
V
PFD
Power-fail Deselect Voltage (M48Z58/58Y)
4.5
4.6
4.75
V
V
PFD
Power-fail Deselect Voltage (M48Z58/58YY)
4.2
4.35
4.5
V
V
SO
Battery Back-up Switchover Voltage
3.0
V
t
DR
(2)
Expected Data Retention Time
10
YEARS
Notes: 1. All voltages referenced to V
SS
.
2. At 25
C
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70
C or 40 to 85
C)
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z58/58Y also has its own Power-fail De-
tect circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
tion. When V
CC
is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low V
CC
. As V
CC
falls below
approximately 3V, the control circuitry connects the
battery which maintains data until valid power re-
turns.
DESCRIPTION (cont'd)
4/17
M48Z58, M48Z58Y
Symbol
Parameter
Min
Max
Unit
t
PD
E or W at V
IH
before Power Down
0
s
t
F
(1)
V
PFD
(max) to V
PFD
(min) V
CC
Fall Time
300
s
t
FB
(2)
V
PFD
(min) to V
SS
V
CC
Fall Time
10
s
t
R
V
PFD
(min) to V
PFD
(max) V
CC
Rise Time
10
s
t
RB
V
SS
to V
PFD
(min) V
CC
Rise Time
1
s
t
REC
(3)
V
PFD
(max) to Inputs Recognized
40
200
ms
Notes: 1. V
PFD
(max) to V
PFD
(min) fall time of less than t
F
may result in deselection/write protection not occurring until 200
s after
V
CC
passes V
PFD
(min).
2. V
PFD
(min) to V
SS
fall time of less than t
FB
may cause corruption of RAM data.
3. t
REC
(min) = 20ms for industrial temperature grade 6 device.
Table 8. Power Down/Up Mode AC Characteristics
(T
A
= 0 to 70
C or 40 to 85
C)
AI01168C
VCC
INPUTS
(PER CONTROL INPUT)
OUTPUTS
DON'T CARE
HIGH-Z
tF
tFB
tR
tPD
tRB
tDR
VALID
VALID
(PER CONTROL INPUT)
RECOGNIZED
RECOGNIZED
VPFD (max)
VPFD (min)
VSO
tREC
Figure 5. Power Down/Up Mode AC Waveforms
5/17
M48Z58, M48Z58Y
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