1/11
August 2001
s
HIGH SPEED :
f
MAX
= 80MHz (TYP.) at V
CC
= 6V
s
LOW POWER DISSIPATION:
I
CC
=2
A(MAX.) at T
A
=25C
s
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 107
DESCRIPTION
The M74HC107 is an high speed CMOS DUAL
J-K FLIP FLOP fabricated with silicon gate
C
2
MOS technology. These flip-flop are edge
sensitive to the clock input and change state on
the negative going transition of the clock pulse.
Each one has independent J, K, CLOCK, and
CLEAR input and Q and Q outputs. CLEAR is
independent of the clock and accomplished by a
logic low on the input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC107
DUAL J-K FLIP FLOP WITH CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HC107B1R
SOP
M74HC107M1R
M74HC107RM13TR
TSSOP
M74HC107TTR
TSSOP
DIP
SOP
M74HC107
2/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
LOGIC DIAGRAM
PIN No
SYMBOL
NAME AND FUNCTION
1, 8, 4, 11
1J, 2J, 1K,
2K
Synchronous Inputs;
Flip-Flop 1 And 2
2, 6
1Q, 2Q
Complement Flip-Flop
Outputs
3, 5
1Q, 2Q
True Flip-Flop Outputs
12, 9
1CK, 2CK
Clock Input
13, 10
1CLR, 2CLR
Asynchronous Reset
Inputs
7
GND
Ground (0V)
14
Vcc
Positive Supply Voltage
INPUTS
OUTPUTS
FUNCTION
CLR
J
K
CK
Q
Q
L
X
X
X
L
H
CLEAR
H
L
L
Q
n
Q
n
NO CHANGE
H
L
H
L
H
----
H
H
L
H
L
----
H
H
H
Q
n
Q
n
TOGGLE
H
X
X
Q
n
Q
n
NO CHANGE
M74HC107
3/11
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
C; derate to 300mW by 10mW/
C from 65
C to 85
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
P
D
Power Dissipation
500(*)
mW
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
t
r
, t
f
Input Rise and Fall Time
V
CC
= 2.0V
0 to 1000
ns
V
CC
= 4.5V
0 to 500
ns
V
CC
= 6.0V
0 to 400
ns
M74HC107
4/11
DC SPECIFICATIONS
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
V
OH
High Level Output
Voltage
2.0
I
O
=-20
A
1.9
2.0
1.9
1.9
V
4.5
I
O
=-20
A
4.4
4.5
4.4
4.4
6.0
I
O
=-20
A
5.9
6.0
5.9
5.9
4.5
I
O
=-4.0 mA
4.18
4.31
4.13
4.10
6.0
I
O
=-5.2 mA
5.68
5.8
5.63
5.60
V
OL
Low Level Output
Voltage
2.0
I
O
=20
A
0.0
0.1
0.1
0.1
V
4.5
I
O
=20
A
0.0
0.1
0.1
0.1
6.0
I
O
=20
A
0.0
0.1
0.1
0.1
4.5
I
O
=4.0 mA
0.17
0.26
0.33
0.40
6.0
I
O
=5.2 mA
0.18
0.26
0.33
0.40
I
I
Input Leakage
Current
6.0
V
I
= V
CC
or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
6.0
V
I
= V
CC
or GND
2
20
40
A
M74HC107
5/11
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6ns)
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per FLIP/
FLOP)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
TLH
t
THL
Output Transition
Time
2.0
30
75
95
110
ns
4.5
8
15
19
22
6.0
7
13
16
19
t
PLH
t
PHL
Propagation Delay
Time (CK - Q, Q)
2.0
48
125
155
190
ns
4.5
14
25
31
38
6.0
12
21
26
32
t
PLH
t
PHL
Propagation Delay
Time (CLR - Q, Q)
2.0
52
140
175
210
ns
4.5
15
28
35
42
6.0
13
24
30
36
f
MAX
Maximum Clock
Frequency
2.0
6.2
23
5.0
4.2
MHz
4.5
31
70
25
21
6.0
37
80
30
25
t
W(H)
t
W(L)
Minimum Pulse
Width (CLOCK)
2.0
20
75
95
110
ns
4.5
5
15
19
22
6.0
4
13
16
19
t
W(L)
Minimum Pulse
Width (CLR)
2.0
20
75
95
110
ns
4.5
5
15
19
22
6.0
4
13
16
19
t
s
Minimum Set-up
Time
2.0
28
75
95
110
ns
4.5
7
15
19
22
6.0
6
13
16
19
t
h
Minimum Hold
Time
2.0
0
0
0
ns
4.5
0
0
0
6.0
0
0
0
t
REM
Minimum Removal
Time (CLR)
2.0
25
30
40
ns
4.5
5
6
8
6.0
5
5
7
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
5.0
5
10
10
10
pF
C
PD
Power Dissipation
Capacitance (note
1)
5.0
32
pF
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