1/12
July 2001
s
HIGH SPEED:
f
MAX
= 84MHz (TYP.) at V
CC
= 6V
s
LOW POWER DISSIPATION:
I
CC
= 4
A(MAX.) at T
A
=25C
s
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
=6mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 173
DESCRIPTION
The M74HC173 is an high speed CMOS QUAD
D-TYPE REGISTER (3-STATE) fabricated with
silicon gate C
2
MOS technology.
This device is composed of a four-bit register
including D-TYPE flip-flops and 3-state buffers.
The four flip-flops are controlled by a common
clock input (CLOCK) and a common reset input
(CLEAR). Signals applied to the data inputs (D
1
-
D
4
) are stored at the respective flip-flops on the
positive going transition of the clock input, only
when both clock control inputs (G1 and G2) are
held low.
The reset feature is asynchronous and active
high. The stored data are provided on each output
only when both output control inputs (M and N) are
held low, otherwise the outputs go to the
high-impedance state.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC173
QUAD D-TYPE REGISTER (3 STATE)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HC173B1R
SOP
M74HC173M1R
M74HC173RM13TR
TSSOP
M74HC173TTR
TSSOP
DIP
SOP
M74HC173
2/12
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
Z : High Impedance
PIN No
SYMBOL
NAME AND FUNCTION
1, 2
M, N
Output Enable Input
(Active Low)
3, 4, 5, 6
1Q to 4Q
3-State Flip-Flop Outputs
7
CLOCK
Clock Input (Low to HIGH,
Edge-triggered)
9, 10
G1, G2
Data Enable Inputs
(Active Low)
14, 13, 12,
11
1D to 4D
Data Inputs
15
CLEAR
Asynchronous Master
Reset (Active High)
8
GND
Ground (0V)
16
V
CC
Positive Supply Voltage
CLEAR
CLOCK
DATA ENABLE
Dn
OUTPUT CONTROL
Qn
G1
G2
M
N
X
X
X
X
X
H
X
Z
X
X
X
X
X
X
H
Z
H
X
X
X
X
L
L
L
L
X
X
X
L
L
Q0
L
H
X
X
L
L
Q0
L
X
H
X
L
L
Q0
L
L
L
H
L
L
H
L
L
L
L
L
L
L
M74HC173
3/12
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
C; derate to 300mW by 10mW/
C from 65
C to 85
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
35
mA
I
CC
or I
GND
DC V
CC
or Ground Current
70
mA
P
D
Power Dissipation
500(*)
mW
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
M74HC173
4/12
RECOMMENDED OPERATING CONDITIONS
DC SPECIFICATIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
t
r
, t
f
Input Rise and Fall Time
V
CC
= 2.0V
0 to 1000
ns
V
CC
= 4.5V
0 to 500
ns
V
CC
= 6.0V
0 to 400
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
V
OH
High Level Output
Voltage
2.0
I
O
=-20
A
1.9
2.0
1.9
1.9
V
4.5
I
O
=-20
A
4.4
4.5
4.4
4.4
6.0
I
O
=-20
A
5.9
6.0
5.9
5.9
4.5
I
O
=-4.0 mA
4.18
4.31
4.13
4.10
6.0
I
O
=-5.2 mA
5.68
5.8
5.63
5.60
V
OL
Low Level Output
Voltage
2.0
I
O
=20
A
0.0
0.1
0.1
0.1
V
4.5
I
O
=20
A
0.0
0.1
0.1
0.1
6.0
I
O
=20
A
0.0
0.1
0.1
0.1
4.5
I
O
=4.0 mA
0.17
0.26
0.33
0.40
6.0
I
O
=5.2 mA
0.18
0.26
0.33
0.40
I
I
Input Leakage
Current
6.0
V
I
= V
CC
or GND
0.1
1
1
A
I
OZ
High Impedance
Output Leakage
Current
6.0
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.5
5.0
10
A
I
CC
Quiescent Supply
Current
6.0
V
I
= V
CC
or GND
4
40
80
A
M74HC173
5/12
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6ns)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
TLH
t
THL
Output Transition
Time
2.0
50
25
60
75
90
ns
4.5
7
12
15
18
6.0
6
10
13
15
t
PLH
t
PHL
Propagation Delay
Time
(CLOCK - Q)
2.0
50
50
115
145
175
ns
4.5
14
23
29
35
6.0
12
20
25
30
2.0
150
65
145
180
220
ns
4.5
18
29
36
44
6.0
15
25
31
37
t
PLH
t
PHL
Propagation Delay
Time
(CLEAR - Q)
2.0
50
50
115
145
175
ns
4.5
14
23
29
35
6.0
12
20
25
30
2.0
150
65
145
180
220
ns
4.5
18
29
36
44
6.0
15
25
31
37
f
MAX
Maximum Clock
Frequency
2.0
50
8.6
20
6.8
5.8
MHz
4.5
43
67
34
29
6.0
51
84
40
34
t
PZL
t
PZH
Output Enable
Time
2.0
50
R
L
= 1 K
50
115
145
175
ns
4.5
14
23
29
35
6.0
12
20
25
30
2.0
150
R
L
= 1 K
65
145
180
220
ns
4.5
18
29
36
44
6.0
15
25
31
37
t
PLZ
t
PHZ
Output Disable
Time
2.0
50
R
L
= 1 K
36
105
130
160
ns
4.5
15
21
26
32
6.0
13
18
22
27
t
W(H)
t
W(L)
Minimum Pulse
Width (CLOCK)
2.0
50
16
75
95
110
ns
4.5
4
15
19
22
6.0
3
13
16
19
t
W(L)
Minimum Pulse
Width (CLEAR)
2.0
50
16
75
95
110
ns
4.5
4
15
19
22
6.0
3
13
16
19
t
s
Minimum Set-up
Time (G1, G2)
2.0
50
40
100
125
150
ns
4.5
10
20
25
30
6.0
9
17
21
26
t
s
Minimum Set-up
Time (D)
2.0
50
24
75
95
110
ns
4.5
6
15
19
22
6.0
5
13
16
19
t
h
Minimum Hold
Time (G1 ,G2, D)
2.0
50
0
0
0
ns
4.5
0
0
0
6.0
0
0
0
t
REM
Minimum Removal
Time
2.0
50
5
5
5
ns
4.5
5
5
5
6.0
5
5
5
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