M54HC259
M74HC259
October 1992
8 BIT ADDRESSABLE LATCH
B1R
(Plastic Package)
ORDER CODES :
M54HC259F1R
M74HC259M1R
M74HC259B1R
M74HC259C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
.
HIGH SPEED
t
PD
= 15 ns (TYP.) at V
CC
= 5 V
.
LOW POWER DISSIPATION
I
CC
= 4
A (MAX.) at T
A
= 25
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL PROPAGATION DELAYS
IOH
= I
OL
= 4 mA (MIN.)
.
BALANCED PRORAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS259
DESCRIPTION
The M54/74HC259 is a high speed CMOS 8 BIT
ADDRESSABLE LATCH fabricated in silicon gate
C
2
MOS technology. It has the same high speed per-
formance of LSTTL combined with true CMOS low
power consumption.
The M54HC259/M74HC259 has single data input
(D) 8 latch outputs (Q0-Q7), 3 address inputs (A, B,
and C), common enable input (E), and a common
CLEAR input. To operate this device as an address-
able latch, data is held on the D input, and the ad-
dress of the latch into which the data is to be entered
is held on the A, B, and C inputs. When ENABLE is
taken low the data flows through to the addresses
output. The data is stored on the positive-going
edge of the ENABLE pulse. All unaddressed latches
will remain unaffected. With ENABLE in the high
state the device is deselected and all latches remain
in their previous state, unaffected by changes on the
data or address inputs. To eliminate the possibility
of entering erroneous data into the latches, the EN-
ABLE should be held high (inactive) while the ad-
dress lines are changing. If ENABLE is held high and
CLEAR is taken low all eight latches are cleared to
the low state. If ENABLE is low all latches except the
addressed latch will be cleared. The addressed
latch will instead follow the D input, effectively imple-
menting a 3-to 8 line decoder.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
1/12
TRUTH TABLE
INPUTS
OUTPUTS OF
ADDRESSED LATCH
EACH OTHER
OUTPUT
FUNCTION
CLEAR
ENABLE
H
L
D
Qi0
ADDRESSABLE LATCH
H
H
Qi0
Qi0
MEMORY
L
L
D
L
8 LINE DEMULTIPLEXER
L
H
L
L
CLEAR ALL BITS TO 'L'
D: The level at the data input
Qi0: The level before the indicated steady state input conditions were established, (i = 0, 1, .....,7).
LOGIC DIAGRAM
SELECT INPUTS
LATCH ADDRESSED
C
B
A
L
L
L
Q0
L
L
H
Q1
L
H
L
Q2
L
H
H
Q3
H
L
L
Q4
H
L
H
Q5
H
H
L
Q6
H
H
H
Q7
M54/M74HC259
2/12
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1, 2, 3
A, B, C
Address Inputs
4, 5, 6, 7, 9,
10, 11, 12
Q0 to Q7
Latch Outputs
13
D
Data Input
14
ENABLE
Latch Enable Input
(Active LOW)
15
CLEAR
Conditional Reset Input
(Active LOW)
8
GND
Ground (0V)
16
V
CC
Positive Supply Voltage
INPUT AND OUTPUT EQUIVALENT CIRCUIT
IEC LOGIC SYMBOL
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Source Sink Current Per Output Pin
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
P
D
Power Dissipation
500 (*)
mW
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
(*) 500 mW:
65
o
C derate to 300 mW by 10mW/
o
C: 65
o
C to 85
o
C
M54/M74HC259
3/12
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature: M54HC Series
M74HC Series
-55 to +125
-40 to +85
o
C
o
C
t
r
, t
f
Input Rise and Fall Time
V
CC
= 2 V
0 to 1000
ns
V
CC
= 4.5 V
0 to 500
V
CC
= 6 V
0 to 400
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
-40 to 85
o
C
74HC
-55 to 125
o
C
54HC
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
V
OH
High Level
Output Voltage
2.0
V
I
=
V
IH
or
V
IL
I
O
=-20
A
1.9
2.0
1.9
1.9
V
4.5
4.4
4.5
4.4
4.4
6.0
5.9
6.0
5.9
5.9
4.5
I
O
=-4.0 mA
4.18
4.31
4.13
4.10
6.0
I
O
=-5.2 mA
5.68
5.8
5.63
5.60
V
OL
Low Level Output
Voltage
2.0
V
I
=
V
IH
or
V
IL
I
O
= 20
A
0.0
0.1
0.1
0.1
V
4.5
0.0
0.1
0.1
0.1
6.0
0.0
0.1
0.1
0.1
4.5
I
O
= 4.0 mA
0.17
0.26
0.33
0.40
6.0
I
O
= 5.2 mA
0.18
0.26
0.33
0.40
I
I
Input Leakage
Current
6.0
V
I
= V
CC
or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
6.0
V
I
= V
CC
or GND
4
40
80
A
M54/M74HC259
4/12
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
-40 to 85
o
C
74HC
-55 to 125
o
C
54HC
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
TLH
t
THL
Output Transition
Time
2.0
30
75
95
110
ns
4.5
8
15
19
22
6.0
7
13
16
19
t
PLH
t
PHL
Propagation
Delay Time
(DATA - Q)
2.0
56
140
175
210
ns
4.5
18
28
35
42
6.0
15
24
30
36
t
PLH
t
PHL
Propagation
Delay Time
(A, B, C - Q)
2.0
76
190
240
285
ns
4.5
24
38
48
57
6.0
20
32
41
48
t
PLH
t
PHL
Propagation
Delay Time
(G - Q)
2.0
57
150
190
225
ns
4.5
19
30
38
45
6.0
16
26
32
38
t
PLH
t
PHL
Propagation
Delay Time
(CLEAR - Q)
2.0
45
115
145
175
ns
4.5
15
23
29
35
6.0
13
20
25
30
t
W(L)
Minimum Pulse
Width
(ENABLE)
2.0
28
75
90
115
ns
4.5
7
15
19
23
6.0
6
13
16
20
t
W(L)
Minimum Pulse
Width
(CLEAR)
2.0
24
75
90
115
ns
4.5
6
15
19
23
6.0
5
13
16
20
t
s
Minimum Set-up
Time
(DATA)
2.0
12
50
60
75
ns
4.5
3
10
12
15
6.0
3
9
11
13
t
s
Minimum Set-up
Time
(A, B, C)
2.0
25
30
40
ns
4.5
5
6
8
6.0
5
5
7
t
h
Minimum Hold
Time
(DATA)
2.0
5
5
5
ns
4.5
5
5
5
6.0
5
5
5
t
h
Minimum Hold
Time
(A, B, C)
2.0
0
0
0
ns
4.5
0
0
0
6.0
0
0
0
C
IN
Input Capacitance
5
10
10
10
pF
C
PD
(*)
Power Dissipation
Capacitance
66
pF
(*) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
M54/M74HC259
5/12
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