1/11
August 2001
s
HIGH SPEED:
t
PD
= 12ns (TYP.) at V
CC
= 6V
s
LOW POWER DISSIPATION:
I
CC
= 4
A(MAX.) at T
A
=25C
s
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 6mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 533
DESCRIPTION
The M74HC533 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C
2
MOS technology.
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input. When the LE is
taken, the Q outputs will be latched at the logic
level of D input data.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while high level the outputs will be in a
high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HC533
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT INVERTING
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HC533B1R
SOP
M74HC533M1R
M74HC533RM13TR
TSSOP
M74HC533TTR
TSSOP
DIP
SOP
M74HC533
2/11
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X: Don't Care
Z: High Impedance
(*): Q Outputs are latched at the time when the LE input is taken low logic level.
LOGIC DIAGRAM
PIN No
SYMBOL
NAME AND FUNCTION
1
OE
3 State Output Enable
Input (Active LOW)
2, 5, 6, 9, 12,
15, 16, 19
Q0 to Q7
3 State Outputs
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
Data Inputs
11
LE
Latch Enable Input
10
GND
Ground (0V)
20
V
CC
Positive Supply Voltage
INPUTS
OUTPUTS
OE
LE
D
Q
H
X
X
Z
L
L
X
NO CHANGE (*)
L
H
L
H
L
H
H
L
M74HC533
3/11
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
C; derate to 300mW by 10mW/
C from 65
C to 85
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
35
mA
I
CC
or I
GND
DC V
CC
or Ground Current
70
mA
P
D
Power Dissipation
500(*)
mW
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
t
r
, t
f
Input Rise and Fall Time
V
CC
= 2.0V
0 to 1000
ns
V
CC
= 4.5V
0 to 500
ns
V
CC
= 6.0V
0 to 400
ns
M74HC533
4/11
DC SPECIFICATIONS
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
V
OH
High Level Output
Voltage
2.0
I
O
=-20
A
1.9
2.0
1.9
1.9
V
4.5
I
O
=-20
A
4.4
4.5
4.4
4.4
6.0
I
O
=-20
A
5.9
6.0
5.9
5.9
4.5
I
O
=-6.0 mA
4.18
4.31
4.13
4.10
6.0
I
O
=-7.8 mA
5.68
5.8
5.63
5.60
V
OL
Low Level Output
Voltage
2.0
I
O
=20
A
0.0
0.1
0.1
0.1
V
4.5
I
O
=20
A
0.0
0.1
0.1
0.1
6.0
I
O
=20
A
0.0
0.1
0.1
0.1
4.5
I
O
=6.0 mA
0.17
0.26
0.33
0.40
6.0
I
O
=7.8 mA
0.18
0.26
0.33
0.40
I
I
Input Leakage
Current
6.0
V
I
= V
CC
or GND
0.1
1
1
A
I
OZ
High Impedance
Output Leakage
Current
6.0
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.5
5
10
A
I
CC
Quiescent Supply
Current
6.0
V
I
= V
CC
or GND
4
40
80
A
M74HC533
5/11
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6ns)
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per Flip
Flop) and the C
PD
when n pcs of Flip Flop operate, can be gained by the following equation: C
PD(TOTAL)
= 22 + 16 x n (pF)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
C
L
(pF)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
TLH
t
THL
Output Transition
Time
2.0
50
25
60
75
90
ns
4.5
7
12
15
18
6.0
6
10
13
15
t
PLH
t
PHL
Propagation Delay
Time
(LE, D - Q)
2.0
50
42
125
155
190
ns
4.5
14
25
31
38
6.0
12
21
26
32
2.0
150
57
175
220
265
ns
4.5
19
35
44
53
6.0
16
30
37
45
t
PZL
t
PZH
High Impedance
Output Enable
Time
2.0
50
R
L
= 1 K
39
125
155
190
ns
4.5
13
25
31
38
6.0
11
21
26
32
2.0
150
R
L
= 1 K
54
175
220
265
ns
4.5
18
35
44
53
6.0
15
30
37
45
t
PLZ
t
PHZ
High Impedance
Output Disable
Time
2.0
50
R
L
= 1 K
30
125
155
190
ns
4.5
14
25
31
38
6.0
13
21
26
32
t
W(H)
Minimum Pulse
Width (LE)
2.0
50
15
75
95
110
ns
4.5
6
15
19
22
6.0
6
13
16
19
t
s
Minimum Set-up
Time
2.0
50
16
50
65
75
ns
4.5
4
10
13
15
6.0
3
9
11
13
t
h
Minimum Hold
Time
2.0
50
5
5
5
ns
4.5
5
5
5
6.0
5
5
5
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
5
10
10
10
pF
C
OUT
Output
Capacitance
10
pF
C
PD
Power Dissipation
Capacitance (note
1)
38
pF
PDF 
ZIP