M54HC595
M74HC595
April 1993
8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE)
B1R
(Plastic Package)
ORDER CODES :
M54HC595F1R
M74HC595M1R
M74HC595B1R
M74HC595C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
.
HIGH SPEED
f
MAX
= 55 MHz (TYP.) AT V
CC
= 5 V
.
LOW POWER DISSIPATION
I
CC
= 4
A (MAX.) AT T
A
= 25
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS FOR QA TO QH
10 LSTTL LOADS FOR QH'
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 6 mA (MIN.) FOR QA TO QH
|I
OH
| = I
OL
= 4 mA (MIN.) FOR QH'
.
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
.
PIN AND FUNCTION COMPATIBLE
WITH LSTTL 54/74LS595
DESCRIPTION
The M54/74HC595 is a high speed CMOS 8-BIT
SHIFT
REGISTERS/OUTPUT
LATCHES
(3-
STATE) fabricated in silicon C
2
MOS technology. It
has the same high speed performance of LSTTL
combined with true CMOS low power consumption.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage reg-
ister. The storage register has 8 3-STATE outputs.
Separate clocks are provided for both the shift reg-
ister and the storage register.
The shift register has a direct-overriding clear, serial
input, and serial output (standard) pins for cascad-
ing. Both the shift register and storage register use
positive-edge triggered clocks. If both clocks are
connected together, the shift register state will al-
ways be one clock pulse ahead of the storage reg-
ister.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
1/13
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
INPUTS
OUTPUT
SI
SCK
SCLR
RCK
G
X
X
X
X
H
QA THRU QH OUTPUTS DISABLE
X
X
X
X
L
QA THRU QH OUTPUTS ENABLE
X
X
L
X
X
SHIFT REGISTER IS CLEARED
L
H
X
X
FIRST STAGE OF S.R. BECOMES "L" OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
H
H
X
X
FIRST STAGE OF S.R. BECOMES "H" OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
X
H
X
X
STATE OF S.R IS NOT CHANGED
X
X
X
X
S.R. DATA IS STORED INTO STORAGE REGISTER
X
X
X
X
STORAGE REGISTER STATE IS NOT CHANGED
X: DON'T CARE
LOGIC DIAGRAM
M54/M74HC595
2/13
LOGIC DIAGRAM
TIMING CHART
M54/M74HC595
3/13
IEC LOGIC SYMBOL
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current Per Output Pin QA-QH
35
mA
I
O
DC Output Current Per Output Pin QH'
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
70
mA
P
D
Power Dissipation
500 (*)
mW
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
(*) 500 mW:
65
o
C derate to 300 mW by 10mW/
o
C: 65
o
C to 85
o
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
2 to 6
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature: M54HC Series
M74HC Series
-55 to +125
-40 to +85
o
C
o
C
t
r
, t
f
Input Rise and Fall Time
V
CC
= 2 V
0 to 1000
ns
V
CC
= 4.5 V
0 to 500
V
CC
= 6 V
0 to 400
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1, 2, 3, 4, 5,
6, 7, 15
QA to QH
Data Outputs
9
QH'
Serial Data Outputs
10
SCLR
Shift Register Clear
Input
11
SCK
Shift Register Clock
Input
13
G
Output Enable Input
14
SI
Serial Data Input
12
RCK
Storage Register Clock
Input
8
GND
Ground (0V)
16
V
CC
Positive Supply Voltage
M54/M74HC595
4/13
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
-40 to 85
o
C
74HC
-55 to 125
o
C
54HC
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
2.0
1.5
1.5
1.5
V
4.5
3.15
3.15
3.15
6.0
4.2
4.2
4.2
V
IL
Low Level Input
Voltage
2.0
0.5
0.5
0.5
V
4.5
1.35
1.35
1.35
6.0
1.8
1.8
1.8
V
OH
High Level
Output Voltage
(for QH' output)
2.0
V
I
=
V
IH
or
V
IL
I
O
=-20
A
1.9
2.0
1.9
1.9
V
4.5
4.4
4.5
4.4
4.4
6.0
5.9
6.0
5.9
5.9
4.5
I
O
=-4.0 mA
4.18
4.31
4.13
4.10
6.0
I
O
=-5.2 mA
5.68
5.8
5.63
5.60
V
OH
High Level
Output Voltage
(for QA to QH
outputs)
2.0
V
I
=
V
IH
or
V
IL
I
O
=-20
A
1.9
2.0
1.9
1.9
V
4.5
4.4
4.5
4.4
4.4
6.0
5.9
6.0
5.9
5.9
4.5
I
O
=-6.0 mA
4.18
4.31
4.13
4.10
6.0
I
O
=-7.8 mA
5.68
5.8
5.63
5.60
V
OL
Low Level Output
Voltage
(for QH' output)
2.0
V
I
=
V
IH
or
V
IL
I
O
= 20
A
0.0
0.1
0.1
0.1
V
4.5
0.0
0.1
0.1
0.1
6.0
0.0
0.1
0.1
0.1
4.5
I
O
= 4.0 mA
0.17
0.26
0.33
0.40
6.0
I
O
= 5.2 mA
0.18
0.26
0.33
0.40
V
OL
Low Level Output
Voltage
(for QA to QH
outputs)
2.0
V
I
=
V
IH
or
V
IL
I
O
= 20
A
0.0
0.1
0.1
0.1
V
4.5
0.0
0.1
0.1
0.1
6.0
0.0
0.1
0.1
0.1
4.5
I
O
= 6.0 mA
0.17
0.26
0.33
0.40
6.0
I
O
= 7.8 mA
0.18
0.26
0.33
0.40
I
I
Input Leakage
Current
6.0
V
I
= V
CC
or GND
0.1
1
1
A
I
OZ
3 State Output
Off State Current
6.0
V
I
= V
IH
or V
IL
V
O
= V
CC
or GND
0.5
5
10
A
I
CC
Quiescent Supply
Current
6.0
V
I
= V
CC
or GND
4
40
80
A
M54/M74HC595
5/13
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