M74HCT646
M74HCT648
October 1993
HCT648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)
HCT646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
B1R
(Plastic Package)
ORDER CODES :
M74HCTXXXM1R
M74HCTXXXB1R
M1R
(Micro Package)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS (top view)
GAB, GAB, CAB,
A, B
SAB, SBA, CBA
.
HIGH SPEED
f
MAX
= 60 MHz (TYP.) AT V
CC
= 5 V
.
LOW POWER DISSIPATION
I
CC
= 4
A (MAX.) AT T
A
= 25
C
.
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 6 mA (MIN.)
.
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
.
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS646/648
DESCRIPTION
The M74HCT646/648 are high speed CMOS
OCTAL BUS TRANSCEIVERS AND REGISTERS,
(3-STATE) fabricated in silicon gate C
2
MOS tech-
nology.
They
have
the
same
high
speed
performance of LSTTL combined with true CMOS
low power consumption. These devices consist of
bus transceiver circuits with 3-state output, D-type
flip-flops, and control circuitry arranged for multi-
plexed transmission of data directly from the input
bus or from the internal registers. Data on the A or
B bus will be clocked into the registers on the low-
to-high transition of the appropriate clock pin (Clock
AB - or Clock BA). Enable (G) and direction (DIR)
pins are provided to control the transceiver function-
s. In the transceiver mode, data present at the
high-impedance port may be stored in either register
or in both. The select controls (Select AB select BA)
can multiplex stored and real-time (transparent
mode) data. The direction control determines which
bus will receive data when enable G is active (low).
In the isolation mode (enable G high), "A" data may
be stored in one register and/or "B" data may be
stored in the other register. When an output function
is disabled, the input function is still enabled and
may be used to store and transmit data. Only one
of the two buses, A or B, may be driven at a time.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.This integrated circuit has input and output
characteristics that are fully compatible with 54/74
LSTTL logic families. M74HCT devices are de-
signed to directly interface HSC
2
MOS systems with
TTL and NMOS components. They are also plug in
replacements for LSTTL devices giving a reduction
of power consumption.
1/12
LOGIC DIAGRAM (HCT648)
Note : In case of M54/74HCT646 output inverter marked * at A bus and B bus are eliminated.
TIMING CHART
M74HCT646/648
2/12
TRUTH TABLE
HCT646 (The truth table for HCT648 is the same as this, but with the outputs inverted)
G
DIR
CAB CBA SAB SBA
A
B
FUNCTION
H
X
INPUTS
INPUTS
Both the A bus and the B bus are inputs
X
X
X
X
Z
Z
The output functions of the A and B bus are disabled
X
X
INPUTS
INPUTS
Both the A and B bus are used for inputs to the
internal flip-flops. Data at the bus will be stored on
low to high transition of the clock inputs
L
H
iNPUTS
OUTPUTS
The A bus are inputs and the B bus are outputs
X
X*
L
X
L
L
The data at the A bus are displayed at the B bus
H
H
X*
L
X
L
L
The data at the A bus are displayed at the B bus.
The data of the A bus are stored to the internal
flip-flop on low to high transition of th clock pulse.
H
H
X
X*
H
X
X
Qn
The data stored to the internal flip-flop are dispayed
at the B bus
X*
H
X
L
L
The data at the A bus are stored to the internal flip-
flop on low to high transition of the clock pulse. The
states of the internal flip-flops output directly to the
B bus
H
H
L
L
OUTPUTS
INPUTS
The A bus are outputs and the B bus are inputs
X*
X
X
L
L
L
The data at the B bus are displayed at the A bus
H
H
X*
X
L
L
L
The data at the B bus are displayed at the A bus.
The data of the B bus are stored to the internal flip-
flop on low to high transition of the clock pulse
H
H
X*
X
X
H
Qn
X
The data stored to the internal flip-flops are
displayed at the B bus
x*
X
H
L
L
the data at the B bus are stored to the internal flip-
flop on low to high transition of the clock pulse. The
states of the internal flip-flops output directly to the
A bus
H
H
X
: DON'T CARE
Z
: HIGH IMPEDANCE
Qn
: THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS
*
: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO HIGH TRANSITION OF
THE CLOCK INPUTS
M74HCT646/648
3/12
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1
CLOCK AB
A to B Clock Input (LOW to HIGH, Edge-Trigged)
2
SELECT AB
Select A to B Source Input
3
DIR
Direction Control Input
4, 5, 6, 7, 8, 9, 10, 11
A1 to A8
A data Inputs/Outputs
20, 19, 18, 17, 16, 15, 14, 13
B1 to B8
B Data Inputs/Outputs
21
G
Output Enable Input (Active LOW)
22
SELECT BA
Select B to A Source Input
23
CLOCK BA
B to A Clock Input (LOW to HIGH, Edge-Triggered)
12
GND
Ground (0V)
24
V
CC
Positive Supply Voltage
IEC LOGIC SYMBOLS
HCT646
HCT648
M74HCT646/648
4/12
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Source Sink Current Per Output Pin
35
mA
I
CC
or I
GND
DC V
CC
or Ground Current
70
mA
P
D
Power Dissipation
500 (*)
mW
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
(*) 500 mW:
65
o
C derate to 300 mW by 10mW/
o
C: 65
o
C to 85
o
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-40 to +85
o
C
t
r
, t
f
Input Rise and Fall Time (V
CC
= 4.5 to 5.5V)
0 to 500
ns
M74HCT646/648
5/12
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