1/15
April 2003
s
HIGH SPEED:
f
MAX
= 60 MHz (TYP.) at V
CC
= 4.5V
s
LOW POWER DISSIPATION:
I
CC
= 4
A(MAX.) at T
A
=25C
s
COMPATIBLE WITH TTL OUTPUTS :
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 6mA (MIN)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 646
DESCRIPTION
The 74HCT646 is an advanced high-speed
CMOS OCTAL BUS TRANSCEIVER AND
REGISTER (3-STATE) fabricated with silicon gate
C
2
MOS technology.
This device consists of bus transceiver circuits
with 3 state, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data
directly from the input bus or from the internal
registers. Data on the A or B bus will be clocked
into register on the low to high transition of the
appropriate clock pin (Clock AB or Clock BA).
Enable (G) and direction (DIR) pins are provided
to control the transceiver functions. In the
transceiver mode, data present at the
high-impedance port may be stored in either
register or in both. The select controls (Select AB
select BA) can multiplex stored and real time
(transparent mode) data. The direction control
determines which bus will receive data when
enable G is active (low). In the isolation mode
(enable G high), "A" data may be stored in one
register and/or "B" data may be stored in the other
register. When an output function is disabled, the
input function is still enabled and may be used to
store and transmit data. Only one of the two
buses, A or B, may be driven at a time.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT646
OCTAL BUS TRANSCEIVER/REGISTER
WITH 3 STATE OUTPUTS
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HCT646B1R
SOP
M74HCT646M1R
M74HCT646RM13TR
TSSOP
M74HCT646TTR
TSSOP
DIP
SOP
M74HCT646
2/15
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
Z : High Impedance
Qn : The data stored to the internal flip-flops by most recent low to high transition of the clock inputs
* : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs.
PIN No
SYMBOL
NAME AND FUNCTION
1
CLOCK AB
A to B Clock Input (LOW
to HIGH, Edge-Triggered)
2
SELECT AB Select A to B Source Input
3
GAB
Direction Control Input
4, 5, 6, 7, 8,
9, 10, 11
A1 to A8
A Data Inputs/Outputs
20, 19, 18,
17, 16, 15,
14, 13
B1 to B8
B Data Inputs/Outputs
21
G
Output Enable Input
(Active LOW)
22
SELECT BA Select B to A Source Input
23
CLOCK BA
B to A Clock Input (LOW
to HIGH, Edge Triggered)
12
GND
Ground (0V)
24
V
CC
Positive Supply Voltage
G
DIR CAB CBA SAB SBA
A
B
FUNCTION
H
X
INPUTS
INPUTS
Both the A bus and the B bus are inputs
X
X
X
X
Z
Z
The Output functions of the A and B bus are disabled
X
X
INPUTS
INPUTS
Both the A and B bus are used for inputs to the internal
flip-flops. Data at the bus will be stored on low to high
transition of the clock inputs.
L
H
INPUTS
OUTPUTS The A bus are inputs and the B bus are outputs
X
X*
L
X
L
L
The data at the A bus are displayed at the B bus
H
H
X*
L
X
L
L
The data at the A bus are displayed at the B bus. The
data of the A bus are stored to internal flip-flop on low
to high transition of the clock pulse
H
H
X
X*
H
X
X
Qn
The data stored to the internal flip-flop are displayed at
the B bus.
X*
H
X
L
L
The data at the A bus are stored to the internal flip-flop
on low to high transition of the clock pulse. The states
of the internal flip-flops output directly to the B bus.
H
H
L
L
OUTPUTS
INPUTS
The B bus are inputs and the A bus are outputs.
X*
X
X
L
L
L
The data at the B bus are displayed at the A bus
H
H
X*
X
L
L
L
The data at the B bus are displayed at the A bus. The
data of the B bus are stored to the internal flip-flop on
low to high transition of the clock pulse.
H
H
X*
X
X
H
Qn
X
The data stored to the internal flip-flops are displayed
at the A bus
X*
X
H
L
L
The data at the B bus are stored to the internal flip-flop
on low to high transition of the clock pulse. The states
of the internal flip-flops output directly to the A bus.
H
H
M74HCT646
4/15
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
C; derate to 300mW by 10mW/
C from 65
C to 85
C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
35
mA
I
CC
or I
GND
DC V
CC
or Ground Current
70
mA
P
D
Power Dissipation
500(*)
mW
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
t
r
, t
f
Input Rise and Fall Time (V
CC
= 4.5 to 5.5V)
0 to 500
ns
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