M74HCT651
M74HCT652
October 1993
HCT652 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)
HCT651 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
.
HIGH SPEED
f
MAX
= 60 MHz (TYP.) AT V
CC
= 5V
.
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2 V (MIN.) AT V
IL
= 0.8V (MAX)
.
LOW POWER DISSIPATION
I
CC
= 4
A (MAX) AT T
A
= 25
o
C
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 6 mA (mIN.)
.
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
.
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS651/652
DESCRIPTION
M74HCT651/652 are high speed CMOS OCTAL
BUS
TRANSCEIVERS
AND
REGISTERS
(3-STATE), fabricated in silicon gate C
2
MOS
technology. They have the same high speed
performance of LSTTL combined with true CMOS
low power consumption. These devices consist of
bus transceiver circuits, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of
data directly from the input bus or from the internal
storage registers. Enable GAB and GBA are
provided to control the transceiver functions. Select
AB and Select BA control pins are provided to select
whether real-time or stored data is transfered. A low
input level selects real-time data, and a high selects
stored data. Data on the A or B bus, or both, can be
stored in the internal D flip-flops by low-to-high
transitions at the appropriate clock pins (CLOCK AB
or CLOCK BA) regardless of the select or enable
control pins. When select AB and select BA are in the
real-time transfer mode, it is also possible to store
data without using the internal D-type flip-flops by
simultaneously enabling GAB and GBA. In this
configuration each output reinforces its input. Thus,
when all other data sources to the two sets of bus
lines are at high impedance, each set of bus lines will
remain at its last state. All inputs are equipped with
protection circuits against static discharge and
transient excess voltage.This integrated circuit has
input and output characteristics that are fully
compatible
with 54/74
LSTTL
logic
families.
M54/74HCT devices are designed to directly
interface HSCMOS systems with TTL and NMOS
components. They are also plug in replacements for
LSTTL devices giving a reduction of power
consumption.
GAB, GAB, CAB,
A, B
SAB, SBA, CBA
B1R
(Plastic Package)
ORDER CODES :
M74HCXXXM1R
M74HCXXXB1R
M1R
(Micro Package)
PIN CONNECTIONS (top view)
1/12
LOGIC DIAGRAM (HCT651)
Note : In case of 74HCT652 output inverter marked * at A bus and B bus are eliminated.
TIMING CHART
M74HCT651/652
2/12
TRUTH TABLE
HCT652 (The truth table for HCT651 is the same as this, but with the outputs inverted)
GAB GBA CAB CBA SAB SBA
A
B
FUNCTION
L
H
INPUTS
INPUTS
Both the A bus and the B bus are inputs
X
X
X
X
Z
Z
The output functions of the A and B bus are disabled
X
X
INPUTS
INPUTS
Both the A and B bus are used for inputs to the
internal flip-flops. Data at the bus will be stored on
low to high transition of the clock inputs
L
L
OUTPUTS
INPUTS
The A bus are outputs and the B bus are inputs
X*
X
X
L
L
L
The data at the B bus are displayed at the A bus
H
H
X*
X
L
L
L
The data at the B bus ar displayed at the A bus.
The data of the B bus are stored to the internal
flip-flop on low to high transition of th clock pulse
H
H
X*
X
X
H
Qn
X
The data stored to the internal flip-flop are dispayed
at the A bus
X*
X
H
L
L
The data at the B bus are stored to the internal flip-
flop on low to high transition of the clock pulse. The
states of the internal flip-flops output directly to the
A bus
H
H
H
H
INPUTS
OUTPUTS
The A bus are inputs and the B bus are outputs
X
X*
L
X
L
L
The data at the A bus are displayed at the B bus
H
H
X*
L
X
L
L
The data at the A bus are displayed at the B bus.
The data of the A bus are stored to the internal flip-
flop on low to high transition of the clock pulse
H
H
X
X*
H
X
X
Qn
The data stored to the internal flip-flops are
displayed at the B bus
X*
H
X
L
L
the data at the A bus are stored to the internal flip-
flop on low to high transition of the clock pulse. The
states of the internal flip-flops output directly to the
B bus
H
H
H
L
OUTPUTS OUTPUTS
Both the A bus and the B bus are outputs
X
X
H
H
Qn
Qn
The data stored to the internal flip-flops are
displayed at the A and B bus respactively
H
H
Qn
Qn
The output at the A bus are displayed at the B bus,
the output at the B bus are displayed at the A bus
respectively
X
: DON'T CARE
Z
: HIGH IMPEDANCE
Qn
: THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS
*
: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO HIGH TRANSITION OF
THE CLOCK INPUTS
M74HCT651/652
3/12
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1
CLOCK AB
A to B Clock Input (LOW to HIGH, Edge-Trigged)
2
SELECT AB
Select A to B Source Input
3
GAB
Direction Control Input
4, 5, 6, 7, 8, 9, 10, 11
A1 to A8
A data Inputs/Outputs
20, 19, 18, 17, 16, 15, 14, 13
B1 to B8
B Data Inputs/Outputs
21
GBA
Output Enable Input (Active LOW)
22
SELECT BA
Select B to A Source Input
23
CLOCK BA
B to A Clock Input (LOW to HIGH, Edge-Triggered)
12
GND
Ground (0V)
24
V
CC
Positive Supply Voltage
IEC LOGIC SYMBOLS
HCT651
HCT652
M74HCT651/652
4/12
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Source Sink Current Per Output Pin
35
mA
I
CC
or I
GND
DC V
CC
or Ground Current
70
mA
P
D
Power Dissipation
500 (*)
mW
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature:
-40 to +85
o
C
t
r
, t
f
Input Rise and Fall Time (V
CC
= 4.5 to 5.5V)
0 to 500
ns
M74HCT651/652
5/12
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