M54HCT74
M74HCT74
February 1993
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
B1R
(Plastic Package)
ORDER CODES :
M54HCT74F1R
M74HCT74M1R
M74HCT74B1R
M74HCT74C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
.
HIGH SPEED
f
MAX
= 53 MHz (TYP.) AT V
CC
= 5 V
.
LOW POWER DISSIPATION
I
CC
= 2
A (MAX.) AT T
A
= 25
C
.
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 4 mA (MIN.)
.
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
.
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS74
The M54/74HCT74 is a high speed CMOS DUAL D
TYPE FLOP WITH PRESET AND CLEAR fabri-
cated in silicon gate C
2
MOS technology. It has the
same high speed performance of LSTTL combined
with true CMOS low power consumption. A signal on
the D INPUT is transferred to the Q OUTPUT during
the positive going transition of the clock pulse.
CLEAR and PRESET are independent of the clock
and accomplished by a low on the appropriate input.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age. This integrated circuit has input and output
characteristics that are fully compatible with 54/74
LSTTL logic families. M54/74HCT devices are de-
signed to directly interface HSC
2
MOS systems with
TTL and NMOS components. They are also plug in
replacements for LSTTL devices giving a reduction
of power consumption.
DESCRIPTION
1/11
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1, 13
1CLR,
2CLR
Asyncronous Reset -
Direct Input
2, 12
1D, 2D
Data Inputs
3, 11
1CK, 2CK
Clock Input
(LOW-to-HIGH, Edge-
Triggered)
4, 10
1PR, 2PR
Asyncronous Set - Direct
Input
5, 9
1Q, 2Q
True Flip-Flop Outpus
6, 8
1Q, 2Q
Complement Flip-Flop
Outputs
7
GND
Ground (0V)
14
V
CC
Positive Supply Voltage
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
PR
D
CK
Q
Q
L
H
X
X
L
H
CLEAR
H
L
X
X
H
L
PRESET
L
L
X
X
H
H
H
H
L
L
H
H
H
H
H
L
H
H
X
Q
n
Q
n
NO CHANGE
X: Don't Care
LOGIC DIAGRAM
M54/M74HCT74
2/11
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature: M54HC Series
M74HC Series
-55 to +125
-40 to +85
o
C
o
C
t
r
, t
f
Input Rise and Fall Time (V
CC
= 4.5 to 5.5V)
0 to 500
ns
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Source Sink Current Per Output Pin
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
P
D
Power Dissipation
500 (*)
mW
T
stg
Storage Temperature
-65 to +150
o
C
T
L
Lead Temperature (10 sec)
300
o
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
(*) 500 mW:
65
o
C derate to 300 mW by 10mW/
o
C: 65
o
C to 85
o
C
M54/M74HCT74
3/11
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
-40 to 85
o
C
74HC
-55 to 125
o
C
54HC
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
4.5
to
5.5
2.0
2.0
2.0
V
V
IL
Low Level Input
Voltage
4.5
to
5.5
0.8
0.8
0.8
V
V
OH
High Level
Output Voltage
4.5
V
I
=
V
IH
or
V
IL
I
O
=-20
A
4.4
4.5
4.4
4.4
V
I
O
=-4.0 mA
4.18
4.31
4.13
4.10
V
OL
Low Level Output
Voltage
4.5
V
I
=
V
IH
or
V
IL
I
O
= 20
A
0.0
0.1
0.1
0.1
V
I
O
= 4.0 mA
0.17
0.26
0.33
0.4
I
I
Input Leakage
Current
5.5
V
I
= V
CC
or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
2
20
40
A
I
CC
Additional worst
case supply
current
5.5
Per Input pin
V
I
= 0.5V or
V
I
= 2.4V
Other Inputs at
V
CC
or GND
I
O
= 0
2.0
2.9
3.0
mA
M54/M74HCT74
4/11
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
Parameter
Test Conditions
Value
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
-40 to 85
o
C
74HC
-55 to 125
o
C
54HC
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
TLH
t
THL
Output Transition
Time
4.5
8
15
19
22
ns
t
PLH
t
PHL
Propagation
Delay Time
(CLOCK - Q)
4.5
21
33
41
50
ns
t
PLH
t
PHL
Propagation
Delay Time
(CL, PR - Q, Q)
4.5
18
30
38
45
ns
f
MAX
Maximum Clock
Frequency
4.5
27
48
22
18
MHz
t
W(H)
t
W(L)
Minimum Pulse
Width
(CLOCK)
4.5
6
15
19
23
ns
t
W(L)
Minimum Pulse
Width
(CL, PR)
4.5
8
15
19
23
ns
t
s
Minimum Set-up
Time
4.5
7
15
19
23
ns
t
h
Minimum Hold
Time
4.5
0
0
0
ns
t
REM
Minimum
Removal Time
(CL, PR)
4.5
1
5
5
6
5
8
ns
C
IN
Input Capacitance
5
10
10
10
pF
C
PD
(*)
Power Dissipation
Capacitance
32
pF
(*) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
/2 (per FLIP/FLOP)
M54/M74HCT74
5/11
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