1/10
August 2001
s
HIGH SPEED :
f
MAX
= 48MHz (TYP.) at V
CC
= 4.5V
s
LOW POWER DISSIPATION:
I
CC
=2
A(MAX.) at T
A
=25C
s
COMPATIBLE WITH TTL OUTPUTS :
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
s
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
s
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
DESCRIPTION
The M74HCT74 is an high speed CMOS DUAL D
TYPE FLIP FLOP WITH CLEAR fabricated with
silicon gate C
2
MOS technology.
A signal on the D INPUT (nD) is transferred on the
Q OUTPUT during the positive going transition of
the clock pulse. CLEAR (CLR) and PRESET (PR)
are independent of the clock and accomplished by
a low on the appropriate input.
The M74HCT74 is designed to directly interface
HSC
2
MOS systems with TTL and NMOS
components.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
M74HCT74
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE
TUBE
T & R
DIP
M74HCT74B1R
SOP
M74HCT74M1R
M74HCT74RM13TR
TSSOP
M74HCT74TTR
TSSOP
DIP
SOP
M74HCT74
2/10
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
TRUTH TABLE
X : Don't Care
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
PIN No
SYMBOL
NAME AND FUNCTION
1,13
1CLR, 2CLR
Asynchronous Reset -
Direct Input
2, 12
1D, 2D
Data Inputs
3, 11
1CK, 2CK
Clock Input
(LOW-to-HIGH,
Edge-Triggered)
4, 10
1PR, 2PR
Asynchronous Set - Direct
Input
5, 9
1Q, 2Q
True Flip-Flop Outputs
6, 8
1Q, 2Q
Complement Flip-Flop
Outputs
7
GND
Ground (0V)
14
Vcc
Positive Supply Voltage
INPUTS
OUTPUTS
FUNCTION
CLR
PR
D
CK
Q
Q
L
H
X
X
L
H
CLEAR
H
L
X
X
H
L
PRESET
L
L
X
X
H
H
----
H
H
L
L
H
----
H
H
H
H
L
----
H
H
X
Q
n
Q
n
NO CHANGE
M74HCT74
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65
C; derate to 300mW by 10mW/
C from 65
C to 85
C
RECOMMENDED OPERATING CONDITIONS
DC SPECIFICATIONS
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
-0.5 to +7
V
V
I
DC Input Voltage
-0.5 to V
CC
+ 0.5
V
V
O
DC Output Voltage
-0.5 to V
CC
+ 0.5
V
I
IK
DC Input Diode Current
20
mA
I
OK
DC Output Diode Current
20
mA
I
O
DC Output Current
25
mA
I
CC
or I
GND
DC V
CC
or Ground Current
50
mA
P
D
Power Dissipation
500(*)
mW
T
stg
Storage Temperature
-65 to +150
C
T
L
Lead Temperature (10 sec)
300
C
Symbol
Parameter
Value
Unit
V
CC
Supply Voltage
4.5 to 5.5
V
V
I
Input Voltage
0 to V
CC
V
V
O
Output Voltage
0 to V
CC
V
T
op
Operating Temperature
-55 to 125
C
t
r
, t
f
Input Rise and Fall Time (V
CC
= 4.5 to 5.5V)
0 to 500
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
V
IH
High Level Input
Voltage
4.5
to
5.5
2.0
2.0
2.0
V
V
IL
Low Level Input
Voltage
4.5
to
5.5
0.8
0.8
0.8
V
V
OH
High Level Output
Voltage
4.5
I
O
=-20
A
4.4
4.5
4.4
4.4
V
I
O
=-4.0 mA
4.18
4.31
4.13
4.10
V
OL
Low Level Output
Voltage
4.5
I
O
=20
A
0.0
0.1
0.1
0.1
V
I
O
=4.0 mA
0.17
0.26
0.33
0.40
I
I
Input Leakage
Current
5.5
V
I
= V
CC
or GND
0.1
1
1
A
I
CC
Quiescent Supply
Current
5.5
V
I
= V
CC
or GND
2
20
40
A
I
CC
Additional Worst
Case Supply
Current
5.5
Per Input pin
V
I
= 0.5V or
V
I
= 2.4V
Other Inputs at
V
CC
or GND
I
O
= 0
2.0
2.9
3.0
mA
M74HCT74
4/10
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6ns)
CAPACITIVE CHARACTERISTICS
1) C
PD
is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/2 (per FLIP/
FLOP)
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
t
TLH
t
THL
Output Transition
Time
4.5
8
15
19
22
ns
t
PLH
t
PHL
Propagation Delay
Time (CLOCK-Q)
4.5
21
33
41
50
ns
t
PLH
t
PHL
Propagation Delay
Time (CL,PR - Q,Q)
4.5
18
30
38
45
ns
f
MAX
Maximum Clock
Frequency
4.5
27
48
22
18
MHz
t
W(H)
t
W(L)
Minimum Pulse
Width (CLOCK)
4.5
6
15
19
23
ns
t
W(L)
Minimum Pulse
Width (CLR, PR)
4.5
8
15
19
23
ns
t
s
Minimum Set-Up
Time
4.5
7
15
19
23
ns
t
h
Minimum Hold
Time
4.5
0
0
0
ns
t
REM
Minimum Removal
Time (CLR, PR to
CLOCK)
4.5
1
5
5
6
5
8
ns
Symbol
Parameter
Test Condition
Value
Unit
V
CC
(V)
T
A
= 25C
-40 to 85C
-55 to 125C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
C
IN
Input Capacitance
5
10
10
10
pF
C
PD
Power Dissipation
Capacitance (note
1)
32
pF
M74HCT74
5/10
TEST CIRCUIT
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
T
= Z
OUT
of pulse generator (typically 50
)
WAVEFORM 1 : PROPAGATION DELAY, MINIMUM SETUP AND HOLD TIME, CK MINIMUM PULSE
WIDTH AND MAXIMUM FREQUENCY (f=1MHz; 50% duty cycle)
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