Document Outline
- FEATURES SUMMARY
- TABLE OF CONTENTS
- SUMMARY DESCRIPTION
- SIGNAL DESCRIPTION
- CONNECTING TO THE SPI BUS
- OPERATING FEATURES
- MEMORY ORGANIZATION
- INSTRUCTIONS
- POWER-UP AND DELIVERY STATE
- INITIAL DELIVERY STATE
- MAXIMUM RATING
- DC and AC PARAMETERS
- PACKAGE MECHANICAL
- Figure 20. PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
- Table 23. PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
- Figure 21. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Outline
- Table 24. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
- Figure 22. TSSOP8 8 lead Thin Shrink Small Outline, Package Outline
- Table 25. TSSOP8 8 lead Thin Shrink Small Outline, Package Mechanical Data
- Figure 23. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Outline
- Table 26. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Mechanical Data
- PART NUMBERING
- REVISION HISTORY
1/39
November 2003
M95640
M95320
64Kbit and 32Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
s
Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
s
Single Supply Voltage:
4.5 to 5.5V for M95xxx
2.5 to 5.5V for M95xxx-W
1.8 to 5.5V for M95xxx-R
s
10MHz, 5MHz or 2MHz clock rate (depending
on ordering options)
s
5ms or 10ms Write Time (depending on
ordering options)
s
Status Register
s
Hardware Protection of the Status Register
s
BYTE and PAGE WRITE (up to 32 Bytes)
s
Self-Timed Programming Cycle
s
Adjustable Size Read-Only EEPROM Area
s
Enhanced ESD Protection
s
More than 100,000 or 1 million Erase/Write
Cycles (depending on ordering options)
s
More than 40 Year Data Retention
Figure 1. Packages
PDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
8
1
TSSOP8 (DW)
169 mil width
TSSOP14 (DL)
169 mil width
M95640, M95320
2/39
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. DIP and SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. TSSOP14 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Active Power and Stand-by Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Protection and Protocol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3/39
M95640, M95320
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Write Enable (WREN) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Write Disable (WRDI) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Write Status Register (WRSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Address Range Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Read from Memory Array (READ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. Byte Write (WRITE) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Page Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Operating Conditions (M95xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Operating Conditions (M95xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Operating Conditions (M95xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2
Figure 16. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. DC Characteristics (M95xxx, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. DC Characteristics (M95xxx, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. DC Characteristics (M95xxx-W, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. DC Characteristics (M95xxx-W, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. DC Characteristics (M95xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. AC Characteristics (M95xxx, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
M95640, M95320
4/39
Table 19. AC Characteristics (M95xxx, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 20. AC Characteristics (M95xxx-W, temperature range 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 21. AC Characteristics (M95xxx-W, temperature range 3) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 22. AC Characteristics (M95xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 19. Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 20. PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 33
Table 23. PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 33
Figure 21. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Outline. . . . 34
Table 24. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
34
Figure 22. TSSOP8 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 35
Table 25. TSSOP8 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 35
Figure 23. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . 36
Table 26. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . 36
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 28. How to Identify Current and Forthcoming Products by the Process Identification Letter 37
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5/39
M95640, M95320
SUMMARY DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are accessed by a high
speed SPI-compatible bus. The memory array is
organized as 8192 x 8 bit (M95640), and 4096 x 8
bit (M95320).
The device is accessed by a simple serial interface
that is SPI-compatible. The bus signals are C, D
and Q, as shown in Table 1 and Figure 2.
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD).
Figure 2. Logic Diagram
Figure 3. DIP and SO Connections
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
Figure 4. TSSOP14 Connections
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
2. NC = Not Connected
Table 1. Signal Names
AI01789C
S
VCC
M95xxx
HOLD
VSS
W
Q
C
D
C Serial
Clock
D
Serial Data Input
Q
Serial Data Output
S
Chip Select
W Write
Protect
HOLD Hold
V
CC
Supply Voltage
V
SS
Ground
D
VSS
C
HOLD
Q
S
VCC
W
AI01790D
M95xxx
1
2
3
4
8
7
6
5
1
AI02346C
2
3
4
14
9
10
8
D
VSS
W
C
S
HOLD
M95xxx
NC
Q
NC
NC
NC
NC
NC
5
6
7
12
13
11
VCC
M95640, M95320
6/39
SIGNAL DESCRIPTION
During all operations, V
CC
must be held stable and
within the specified valid range: V
CC
(min) to
V
CC
(max).
All of the input and output signals must be held
High or Low (according to voltages of V
IH
, V
OH
, V
IL
or V
OL
, as specified in Tables 13 to 17). These sig-
nals are described next.
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Stand-
by mode. Driving Chip Select (S) Low enables the
device, placing it in the active power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don't Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against Write instructions (as
specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and
must be stable during all write operations.
7/39
M95640, M95320
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 5 shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
Figure 5. Bus Master and Memory Devices on the SPI Bus
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SPI Modes
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 6, is the clock polarity when the bus mas-
ter is in Stand-by mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
AI03746D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
SDO
SDI
SCK
C
Q
D
S
SPI Memory
Device
C
Q
D
S
SPI Memory
Device
C
Q
D
S
CS3
CS2
CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
HOLD
W
HOLD
W
HOLD
M95640, M95320
8/39
Figure 6. SPI Modes Supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
9/39
M95640, M95320
OPERATING FEATURES
Power-up
When the power supply is turned on, V
CC
rises
from V
SS
to V
CC
.
During this time, the Chip Select (S) must be al-
lowed to follow the V
CC
voltage. It must not be al-
lowed to float, but should be connected to V
CC
via
a suitable pull-up resistor.
As a built in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
Power On Reset: V
CC
Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V
CC
has reached the POR
threshold value, and all operations are disabled
the device will not respond to any command. In the
same way, when V
CC
drops from the operating
voltage, below the POR threshold value, all oper-
ations are disabled and the device will not respond
to any command.
A stable and valid V
CC
must be applied before ap-
plying any logic signal.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage applied on V
CC
.
Active Power and Stand-by Power Modes
When Chip Select (S) is Low, the device is en-
abled, and in the Active Power mode. The device
consumes I
CC
, as specified in Tables 13 to 17.
When Chip Select (S) is High, the device is dis-
abled. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Stand-by
Power mode, and the device consumption drops
to I
CC1
.
Hold Condition
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don't Care.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the de-
vice while it is in the Hold condition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in Figure
7).
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
Figure 7 also shows what happens if the rising and
falling edges are not timed to coincide with Serial
Clock (C) being Low.
Figure 7. Hold Condition Activation
AI02029D
HOLD
C
Hold
Condition
Hold
Condition
M95640, M95320
10/39
Status Register
Figure 8 shows the position of the Status Register
in the control logic of the device. The Status Reg-
ister contains a number of status and control bits
that can be read or set (as appropriate) by specific
instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
Table 2. Status Register Format
Data Protection and Protocol Control
Non-volatile memory devices can be used in envi-
ronments that are particularly noisy, and within ap-
plications that could experience problems if
memory bytes are corrupted. Consequently, the
device features the following data protection
mechanisms:
s
Write and Write Status Register instructions are
checked that they consist of a number of clock
pulses that is a multiple of eight, before they are
accepted for execution.
s
All instructions that modify data must be
preceded by a Write Enable (WREN) instruction
to set the Write Enable Latch (WEL) bit . This bit
is returned to its reset state by the following
events:
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction
completion
Write (WRITE) instruction completion
s
The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only. This
is the Software Protected Mode (SPM).
s
The Write Protect (W) signal allows the Block
Protect (BP1, BP0) bits to be protected. This is
the Hardware Protected Mode (HPM).
For any instruction to be accepted, and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) for the last bit of the in-
struction, and before the next rising edge of Serial
Clock (C).
Two points need to be noted in the previous sen-
tence:
The `last bit of the instruction' can be the eighth
bit of the instruction code, or the eighth bit of a
data byte, depending on the instruction (except
for Read Status Register (RDSR) and Read
(READ) instructions).
The `next rising edge of Serial Clock (C)' might
(or might not) be the next bus transaction for
some other device on the SPI bus.
Table 3. Write-Protected Block Size
b7 b0
SRWD
0 0 0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
Status Register Bits
Protected Block
Array Addresses Protected
BP1 BP0
M95640
M95320
0 0
none
none
none
0
1
Upper quarter
1800h - 1FFFh
0C00h - 0FFFh
1
0
Upper half
1000h - 1FFFh
0800h - 0FFFh
1
1
Whole memory
0000h - 1FFFh
0000h - 0FFFh
11/39
M95640, M95320
MEMORY ORGANIZATION
The memory is organized as shown in Figure 8.
Figure 8. Block Diagram
AI01272C
HOLD
S
W
Control Logic
High Voltage
Generator
I/O Shift Register
Address Register
and Counter
Data
Register
1 Page
X Decoder
Y Decoder
C
D
Q
Size of the
Read only
EEPROM
area
Status
Register
M95640, M95320
12/39
INSTRUCTIONS
Each instruction starts with a single-byte code, as
summarized in Table 4.
If an invalid instruction is sent (one not contained
in Table 4), the device automatically deselects it-
self.
Table 4. Instruction Set
Figure 9. Write Enable (WREN) Sequence
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.
As shown in Figure 9, to send this instruction to the
device, Chip Select (S) is driven Low, and the bits
of the instruction byte are shifted in, on Serial Data
Input (D). The device then enters a wait state. It
waits for a the device to be deselected, by Chip
Select (S) being driven High.
Instruc
tion
Description
Instruction
Format
WREN
Write Enable
0000 0110
WRDI Write
Disable
0000
0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
C
D
AI02281E
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
13/39
M95640, M95320
Figure 10. Write Disable (WRDI) Sequence
Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in Figure 10, to send this instruction to
the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).
The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
C
D
AI03750D
S
Q
2
1
3
4
5
6
7
High Impedance
0
Instruction
M95640, M95320
14/39
Figure 11. Read Status Register (RDSR) Sequence
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Write or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register con-
tinuously, as shown in Figure 11.
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register in-
struction is accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in Table 2) be-
comes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) be-
come read-only bits and the Write Status Register
(WRSR) instruction is no longer accepted for exe-
cution.
C
D
S
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15
Instruction
0
AI02031E
Q
7
6
5
4
3
2
1
0
Status Register Out
High Impedance
MSB
7
6
5
4
3
2
1
0
Status Register Out
MSB
7
15/39
M95640, M95320
Figure 12. Write Status Register (WRSR) Sequence
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 12.
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches in the eighth
bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status
Register (WRSR) instruction is not executed. As
soon as Chip Select (S) is driven High, the self-
timed Write Status Register cycle (whose duration
is t
W
) is initiated. While the Write Status Register
cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 dur-
ing the self-timed Write Status Register cycle, and
is 0 when it is completed. When the cycle is com-
pleted, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in Table 2.
The Write Status Register (WRSR) instruction also
allows the user to set or reset the Status Register
Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected Mode (HPM). The Write Status Register
(WRSR) instruction is not executed once the Hard-
ware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable
(SRWD) and Block Protect (BP1, BP0) bits are fro-
zen at their current values from just before the
start of the execution of Write Status Register
(WRSR) instruction. The new, updated, values
take effect at the moment of completion of the ex-
ecution of Write Status Register (WRSR) instruc-
tion.
C
D
AI02282D
S
Q
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15
High Impedance
Instruction
Status
Register In
0
7
6
5
4
3
2
0
1
MSB
M95640, M95320
16/39
Table 5. Protection Modes
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 3.
The protection features of the device are summa-
rized in Table 3.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whether Write Protect
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the state of
Write Protect (W):
If Write Protect (W) is driven High, it is possible
to write to the Status Register provided that the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
If Write Protect (W) is driven Low, it is
not
pos-
sible to write to the Status Register
even
if the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
(Attempts to write to the Status Register are re-
jected, and are not accepted for execution). As
a consequence, all the data bytes in the memo-
ry area that are software protected (SPM) by the
Block Protect (BP1, BP0) bits of the Status Reg-
ister, are also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
or by driving Write Protect (W) Low after setting
the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP1, BP0) bits of
the Status Register, can be used.
Table 6. Address Range Bits
Note: 1. b15 to b13 are Don't Care on the M95640.
b15 to b12 are Don't Care on the M95320.
W
Signal
SRWD
Bit
Mode
Write Protection of the
Status Register
Memory Content
Protected Area
1
Unprotected Area
1
1
0
Software
Protected
(SPM)
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
The values in the BP1
and BP0 bits can be
changed
Write Protected
Ready to accept Write
instructions
0
0
1
1
0
1
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the BP1
and BP0 bits cannot be
changed
Write Protected
Ready to accept Write
instructions
Device M95640
M95320
Address Bits
A12-A0
A11-A0
17/39
M95640, M95320
Figure 13. Read from Memory Array (READ) Sequence
Note: Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care.
Read from Memory Array (READ)
As shown in Figure 13, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address bytes are
then shifted in, on Serial Data Input (D). The ad-
dress is loaded into an internal address register,
and the byte of data at that address is shifted out,
on Serial Data Output (Q).
If Chip Select (S) continues to be driven Low, the
internal address register is automatically incre-
mented, and the byte of data at the new address is
shifted out.
When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruc-
tion.
The Read cycle is terminated by driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not execut-
ed, if a Write cycle is currently in progress.
C
D
AI01793D
S
Q
15
2
1
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27
14 13
3
2
1
0
28 29 30
7
6
5
4
3
1
7
0
High Impedance
Data Out 1
Instruction
16-Bit Address
0
MSB
MSB
2
31
Data Out 2
M95640, M95320
18/39
Figure 14. Byte Write (WRITE) Sequence
Note: Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care.
Write to Memory Array (WRITE)
As shown in Figure 14, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High at a byte boundary of the input data.
In the case of Figure 14, this occurs after the
eighth bit of the data byte has been latched in, in-
dicating that the instruction is being used to write
a single byte. The self-timed Write cycle starts,
and continues for a period t
WC
(as specified in Ta-
bles 18 to 22), at the end of which the Write in
Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven
Low, as shown in Figure 15, the next byte of input
data is shifted in, so that more than a single byte,
starting from the given address towards the end of
the same page, can be written in a single internal
Write cycle.
Each time a new data byte is shifted in, the least
significant bits of the internal address counter are
incremented. If the number of data bytes sent to
the device exceeds the page boundary, the inter-
nal address counter rolls over to the beginning of
the page, and the previous data there are overwrit-
ten with the incoming data. (The page size of
these devices is 32 bytes).
The instruction is not accepted, and is not execut-
ed, under the following conditions:
if the Write Enable Latch (WEL) bit has not been
set to 1 (by executing a Write Enable instruction
just before)
if a Write cycle is already in progress
if the device has not been deselected, by Chip
Select (S) being driven High, at a byte boundary
(after the eighth bit, b0, of the last data byte that
has been latched in)
if the addressed page is in the region protected
by the Block Protect (BP1 and BP0) bits.
C
D
AI01795D
S
Q
15
2
1
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27
14 13
3
2
1
0
28 29 30
High Impedance
Instruction
16-Bit Address
0
7
6
5
4
3
2
0
1
Data Byte
31
19/39
M95640, M95320
Figure 15. Page Write (WRITE) Sequence
Note: Depending on the memory size, as shown in Table 6, the most significant address bits are Don't Care.
C
D
AI01796D
S
34
33
35 36 37 38 39 40 41 42
44 45 46 47
32
C
D
S
15
2
1
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27
14 13
3
2
1
0
28 29 30
Instruction
16-Bit Address
0
7
6
5
4
3
2
0
1
Data Byte 1
31
43
7
6
5
4
3
2
0
1
Data Byte 2
7
6
5
4
3
2
0
1
Data Byte 3
6
5
4
3
2
0
1
Data Byte N
M95640, M95320
20/39
POWER-UP AND DELIVERY STATE
Power-up State
After Power-up, the device is in the following state:
Stand-by mode
deselected (after Power-up, a falling edge is re-
quired on Chip Select (S) before any instruc-
tions can be started).
not in the Hold Condition
the Write Enable Latch (WEL) is reset to 0
Write In Progress (WIP) is reset to 0
the SRWD, BP1 and BP0 bits of the Status Regis-
ter are unchanged from the previous power-down
(they are non-volatile bits).
INITIAL DELIVERY STATE
The device is delivered with the memory array set
at all 1s (FFh). The Status Register Write Disable
(SRWD) and Block Protect (BP1 and BP0) bits are
initialized to 0.
21/39
M95640, M95320
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 7. Absolute Maximum Ratings
Note: 1. Compliant with the ECOPACK
7191395 specifiication for lead-free soldering processes
2. No longer than 10 seconds
3. Not exceeding 250C for more than 30 seconds, and peaking at 260C
4. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500
, R2=500
)
Symbol
Parameter
Min.
Max.
Unit
T
STG
Storage Temperature
65
150
C
T
LEAD
Lead Temperature during Soldering
1
PDIP
SO
TSSOP
260
2
260
3
260
3
C
V
O
Output Voltage
0.45
V
CC
+0.6
V
V
I
Input Voltage
0.45
6.5
V
V
CC
Supply Voltage
0.3
6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
4
4000
4000
V
M95640, M95320
22/39
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 8. Operating Conditions (M95xxx)
Table 9. Operating Conditions (M95xxx-W)
Table 10. Operating Conditions (M95xxx-R)
Note: 1. This product is under development. For more information, please contact your nearest ST sales office.
Table 11. AC Measurement Conditions
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 16. AC Measurement I/O Waveform
Symbol
Parameter
Min.
Max.
Unit
V
CC
Supply Voltage
4.5
5.5
V
T
A
Ambient Operating Temperature (range 6)
40
85
C
Ambient Operating Temperature (range 3)
40
125
C
Symbol
Parameter
Min.
Max.
Unit
V
CC
Supply Voltage
2.5
5.5
V
T
A
Ambient Operating Temperature (range 6)
40
85
C
Ambient Operating Temperature (range 3)
40
125
C
Symbol
Parameter
1
Min.
Max.
Unit
V
CC
Supply Voltage
1.8
5.5
V
T
A
Ambient Operating Temperature
40
85
C
Symbol
Parameter
Min.
Max.
Unit
C
L
Load Capacitance
100
pF
Input Rise and Fall Times
50
ns
Input Pulse Voltages
0.2V
CC
to 0.8V
CC
V
Input and Output Timing Reference Voltages
0.3V
CC
to 0.7V
CC
V
AI00825B
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
23/39
M95640, M95320
Table 12. Capacitance
Note: Sampled only, not 100% tested, at T
A
=25C and a frequency of 5 MHz.
Table 13. DC Characteristics (M95xxx, temperature range 6)
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Current product: identified by Process Identification letter S.
3. New product: identified by Process Identification letter V.
Symbol
Parameter
Test Condition
Min
.
Max
.
Unit
C
OUT
Output Capacitance (Q)
V
OUT
= 0V
8
pF
C
IN
Input Capacitance (D)
V
IN
= 0V
8
pF
Input Capacitance (other pins)
V
IN
= 0V
6
pF
Symbol
Parameter
Test Condition
Min.
Max.
Unit
I
LI
Input Leakage Current
V
IN
= V
SS
or
V
CC
2
A
I
LO
Output Leakage Current
S = V
CC
, V
OUT
= V
SS
or
V
CC
2
A
I
CC
Supply Current
C = 0.1V
CC
/0.9V
CC
at 5MHz,
V
CC
= 5 V, Q = open, Current Product
2
4
mA
C = 0.1V
CC
/0.9V
CC
at 10MHz,
V
CC
= 5 V, Q = open, New Product
3
5
mA
I
CC1
Supply Current
(Stand-by)
S = V
CC
, V
CC
= 5 V,
V
IN
= V
SS
or
V
CC
, Current Product
2
10
A
S = V
CC
, V
CC
= 5 V,
V
IN
= V
SS
or
V
CC
, New Product
3
2
A
V
IL
Input Low Voltage
0.45
0.3 V
CC
V
V
IH
Input High Voltage
0.7 V
CC
V
CC
+1
V
V
OL
1
Output Low Voltage
I
OL
= 2 mA, V
CC
= 5 V
0.4
V
V
OH
1
Output High Voltage
I
OH
= 2 mA, V
CC
= 5 V
0.8 V
CC
V
M95640, M95320
24/39
Table 14. DC Characteristics (M95xxx, temperature range 3)
Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.
2. Current product: identified by Process Identification letter S.
3. New product: identified by Process Identification letter B.
Table 15. DC Characteristics (M95xxx-W, temperature range 6)
Note: 1. Current product: identified by Process Identification letter S.
2. New product: identified by Process Identification letter V.
Symbol
Parameter
Test Condition
Min.
Max.
Unit
I
LI
Input Leakage Current
V
IN
= V
SS
or
V
CC
2
A
I
LO
Output Leakage Current
S = V
CC
, V
OUT
= V
SS
or
V
CC
2
A
I
CC
Supply Current
C = 0.1V
CC
/0.9V
CC
at 2 MHz,
V
CC
= 5 V, Q = open, Current Product
2
2
mA
C = 0.1V
CC
/0.9V
CC
at 5 MHz,
V
CC
= 5 V, Q = open, New Product
3
4
mA
I
CC1
Supply Current
(Stand-by)
S = V
CC
, V
CC
= 5 V,
V
IN
= V
SS
or
V
CC
, Current Product
2
20
A
S = V
CC
, V
CC
= 5 V,
V
IN
= V
SS
or
V
CC
, New Product
3
5
A
V
IL
Input Low Voltage
0.45
0.3 V
CC
V
V
IH
Input High Voltage
0.7 V
CC
V
CC
+1
V
V
OL
1
Output Low Voltage
I
OL
= 2 mA, V
CC
= 5 V
0.4
V
V
OH
1
Output High Voltage
I
OH
= 2 mA, V
CC
= 5 V
0.8 V
CC
V
Symbol
Parameter
Test Condition
Min.
Max.
Unit
I
LI
Input Leakage Current
V
IN
= V
SS
or
V
CC
2
A
I
LO
Output Leakage Current
S = V
CC
, V
OUT
= V
SS
or
V
CC
2
A
I
CC
Supply Current
C = 0.1V
CC
/0.9V
CC
at 2 MHz,
V
CC
= 2.5 V, Q = open, Current Product
1
2
mA
C = 0.1V
CC
/0.9V
CC
at 5 MHz,
V
CC
= 2.5 V, Q = open, New Product
2
3
mA
I
CC1
Supply Current
(Stand-by)
S = V
CC
, V
CC
= 2.5 V,
V
IN
= V
SS
or
V
CC
, Current Product
1
2
A
S = V
CC
, V
CC
= 2.5 V
V
IN
= V
SS
or
V
CC
, New Product
2
1
A
V
IL
Input Low Voltage
0.45
0.3 V
CC
V
V
IH
Input High Voltage
0.7 V
CC
V
CC
+1
V
V
OL
Output Low Voltage
I
OL
= 1.5 mA, V
CC
= 2.5 V
0.4
V
V
OH
Output High Voltage
I
OH
= 0.4 mA, V
CC
= 2.5 V
0.8 V
CC
V
25/39
M95640, M95320
Table 16. DC Characteristics (M95xxx-W, temperature range 3)
Note: New product: identified by Process Identification letter B.
Table 17. DC Characteristics (M95xxx-R)
Note: 1. This product is under qualification. For more infomation, please contact your nearest ST sales office.
2. Preliminary data.
Symbol
Parameter
Test Condition
Min.
Max.
Unit
I
LI
Input Leakage Current
V
IN
= V
SS
or
V
CC
2
A
I
LO
Output Leakage Current
S = V
CC
, V
OUT
= V
SS
or
V
CC
2
A
I
CC
Supply Current
C = 0.1V
CC
/0.9V
CC
at 5 MHz,
V
CC
= 2.5 V, Q = open
3
mA
I
CC1
Supply Current
(Stand-by)
S = V
CC
, V
CC
= 2.5 V, V
IN
= V
SS
or
V
CC
2
A
V
IL
Input Low Voltage
0.45
0.3 V
CC
V
V
IH
Input High Voltage
0.7 V
CC
V
CC
+1
V
V
OL
Output Low Voltage
I
OL
= 1.5 mA, V
CC
= 2.5 V
0.4
V
V
OH
Output High Voltage
I
OH
= 0.4 mA, V
CC
= 2.5 V
0.8 V
CC
V
Symbol
Parameter
Test Condition
1
Min.
2
Max.
2
Unit
I
LI
Input Leakage Current
V
IN
= V
SS
or
V
CC
2
A
I
LO
Output Leakage Current
S = V
CC
, V
OUT
= V
SS
or
V
CC
2
A
I
CC
Supply Current
C = 0.1V
CC
/0.9V
CC
at 2 MHz,
V
CC
= 1.8 V, Q = open
1
mA
I
CC1
Supply Current
(Stand-by)
S = V
CC
, V
IN
= V
SS
or
V
CC
, V
CC
= 1.8 V
1
A
V
IL
Input Low Voltage
0.45
0.3 V
CC
V
V
IH
Input High Voltage
0.7 V
CC
V
CC
+1
V
V
OL
Output Low Voltage
I
OL
= 0.15 mA, V
CC
= 1.8 V
0.3
V
V
OH
Output High Voltage
I
OH
= 0.1 mA, V
CC
= 1.8 V
0.8 V
CC
V
M95640, M95320
26/39
Table 18. AC Characteristics (M95xxx, temperature range 6)
Note: 1. t
CH
+ t
CL
1 / f
C
.
2. Value guaranteed by characterization, not 100% tested in production.
3. Current product: identified by Process Identification letter S.
4. New product: identified by Process Identification letter V.
Test conditions specified in Table 11 and Table 8
Symbol
Alt.
Parameter
Min.
3
Max.
3
Min.
4
Max.
4
Unit
f
C
f
SCK
Clock Frequency
D.C.
5
D.C.
10
MHz
t
SLCH
t
CSS1
S Active Setup Time
90
15
ns
t
SHCH
t
CSS2
S Not Active Setup Time
90
15
ns
t
SHSL
t
CS
S Deselect Time
100
40
ns
t
CHSH
t
CSH
S Active Hold Time
90
25
ns
t
CHSL
S Not Active Hold Time
90
15
ns
t
CH
1
t
CLH
Clock High Time
90
40
ns
t
CL
1
t
CLL
Clock Low Time
90
40
ns
t
CLCH
2
t
RC
Clock Rise Time
1
1
s
t
CHCL
2
t
FC
Clock Fall Time
1
1
s
t
DVCH
t
DSU
Data In Setup Time
20
15
ns
t
CHDX
t
DH
Data In Hold Time
30
15
ns
t
HHCH
Clock Low Hold Time after HOLD not Active
70
15
ns
t
HLCH
Clock Low Hold Time after HOLD Active
40
20
ns
t
CHHL
Clock High Set-up Time before HOLD Active
60
30
ns
t
CHHH
Clock High Set-up Time before HOLD not
Active
60
30
ns
t
SHQZ
2
t
DIS
Output Disable Time
100
25
ns
t
CLQV
t
V
Clock Low to Output Valid
60
25
ns
t
CLQX
t
HO
Output Hold Time
0
0
ns
t
QLQH
2
t
RO
Output Rise Time
50
20
ns
t
QHQL
2
t
FO
Output Fall Time
50
20
ns
t
HHQX
2
t
LZ
HOLD High to Output Low-Z
50
25
ns
t
HLQZ
2
t
HZ
HOLD Low to Output High-Z
100
25
ns
t
W
t
WC
Write Time
10
5
ms
27/39
M95640, M95320
Table 19. AC Characteristics (M95xxx, temperature range 3)
Note: 1. t
CH
+ t
CL
1 / f
C
.
2. Value guaranteed by characterization, not 100% tested in production.
3. Current product: identified by Process Identification letter S.
4. New product: identified by Process Identification letter B.
Test conditions specified in Table 11 and Table 8
Symbol
Alt.
Parameter
Min.
3
Max.
3
Min.
4
Max.
4
Unit
f
C
f
SCK
Clock Frequency
D.C.
2
D.C.
5
MHz
t
SLCH
t
CSS1
S Active Setup Time
200
90
ns
t
SHCH
t
CSS2
S Not Active Setup Time
200
90
ns
t
SHSL
t
CS
S Deselect Time
200
100
ns
t
CHSH
t
CSH
S Active Hold Time
200
90
ns
t
CHSL
S Not Active Hold Time
200
90
ns
t
CH
1
t
CLH
Clock High Time
200
90
ns
t
CL
1
t
CLL
Clock Low Time
200
90
ns
t
CLCH
2
t
RC
Clock Rise Time
1
1
s
t
CHCL
2
t
FC
Clock Fall Time
1
1
s
t
DVCH
t
DSU
Data In Setup Time
40
20
ns
t
CHDX
t
DH
Data In Hold Time
50
30
ns
t
HHCH
Clock Low Hold Time after HOLD not Active
140
70
ns
t
HLCH
Clock Low Hold Time after HOLD Active
90
40
ns
t
CHHL
Clock High Set-up Time before HOLD Active
120
70
ns
t
CHHH
Clock High Set-up Time before HOLD not
Active
120
70
ns
t
SHQZ
2
t
DIS
Output Disable Time
250
100
ns
t
CLQV
t
V
Clock Low to Output Valid
150
60
ns
t
CLQX
t
HO
Output Hold Time
0
0
ns
t
QLQH
2
t
RO
Output Rise Time
100
50
ns
t
QHQL
2
t
FO
Output Fall Time
100
50
ns
t
HHQX
2
t
LZ
HOLD High to Output Low-Z
100
50
ns
t
HLQZ
2
t
HZ
HOLD Low to Output High-Z
250
100
ns
t
W
t
WC
Write Time
10
5
ms
M95640, M95320
28/39
Table 20. AC Characteristics (M95xxx-W, temperature range 6)
Note: 1. t
CH
+ t
CL
1 / f
C
.
2. Value guaranteed by characterization, not 100% tested in production.
3. Current product: identified by Process Identification letter S.
4. New product: identified by Process Identification letter V.
Test conditions specified in Table 11 and Table 9
Symbol
Alt.
Parameter
Min.
3
Max.
3
Min.
4
Max.
4
Unit
f
C
f
SCK
Clock Frequency
D.C.
2
D.C.
5
MHz
t
SLCH
t
CSS1
S Active Setup Time
200
90
ns
t
SHCH
t
CSS2
S Not Active Setup Time
200
90
ns
t
SHSL
t
CS
S Deselect Time
200
100
ns
t
CHSH
t
CSH
S Active Hold Time
200
90
ns
t
CHSL
S Not Active Hold Time
200
90
ns
t
CH
1
t
CLH
Clock High Time
200
90
ns
t
CL
1
t
CLL
Clock Low Time
200
90
ns
t
CLCH
2
t
RC
Clock Rise Time
1
1
s
t
CHCL
2
t
FC
Clock Fall Time
1
1
s
t
DVCH
t
DSU
Data In Setup Time
40
20
ns
t
CHDX
t
DH
Data In Hold Time
50
30
ns
t
HHCH
Clock Low Hold Time after HOLD not Active
140
70
ns
t
HLCH
Clock Low Hold Time after HOLD Active
90
40
ns
t
CHHL
Clock High Set-up Time before HOLD Active
120
60
ns
t
CHHH
Clock High Set-up Time before HOLD not
Active
120
60
ns
t
SHQZ
2
t
DIS
Output Disable Time
250
100
ns
t
CLQV
t
V
Clock Low to Output Valid
150
60
ns
t
CLQX
t
HO
Output Hold Time
0
0
ns
t
QLQH
2
t
RO
Output Rise Time
100
50
ns
t
QHQL
2
t
FO
Output Fall Time
100
50
ns
t
HHQX
2
t
LZ
HOLD High to Output Low-Z
100
50
ns
t
HLQZ
2
t
HZ
HOLD Low to Output High-Z
250
100
ns
t
W
t
WC
Write Time
10
5
ms
29/39
M95640, M95320
Table 21. AC Characteristics (M95xxx-W, temperature range 3)
Note: 1. t
CH
+ t
CL
1 / f
C
.
2. Value guaranteed by characterization, not 100% tested in production.
3. New product: identified by Process Identification letter B.
Test conditions specified in Table 11 and Table 9
Symbol
Alt.
Parameter
Min.
Max.
Unit
f
C
f
SCK
Clock Frequency
D.C.
5
MHz
t
SLCH
t
CSS1
S Active Setup Time
90
ns
t
SHCH
t
CSS2
S Not Active Setup Time
90
ns
t
SHSL
t
CS
S Deselect Time
100
ns
t
CHSH
t
CSH
S Active Hold Time
90
ns
t
CHSL
S Not Active Hold Time
90
ns
t
CH
1
t
CLH
Clock High Time
90
ns
t
CL
1
t
CLL
Clock Low Time
90
ns
t
CLCH
2
t
RC
Clock Rise Time
1
s
t
CHCL
2
t
FC
Clock Fall Time
1
s
t
DVCH
t
DSU
Data In Setup Time
20
ns
t
CHDX
t
DH
Data In Hold Time
30
ns
t
HHCH
Clock Low Hold Time after HOLD not Active
70
ns
t
HLCH
Clock Low Hold Time after HOLD Active
40
ns
t
CHHL
Clock High Set-up Time before HOLD Active
60
ns
t
CHHH
Clock High Set-up Time before HOLD not Active
60
ns
t
SHQZ
2
t
DIS
Output Disable Time
100
ns
t
CLQV
t
V
Clock Low to Output Valid
60
ns
t
CLQX
t
HO
Output Hold Time
0
ns
t
QLQH
2
t
RO
Output Rise Time
50
ns
t
QHQL
2
t
FO
Output Fall Time
50
ns
t
HHQX
2
t
LZ
HOLD High to Output Low-Z
50
ns
t
HLQZ
2
t
HZ
HOLD Low to Output High-Z
100
ns
t
W
t
WC
Write Time
5
ms
M95640, M95320
30/39
Table 22. AC Characteristics (M95xxx-R)
Note: 1. t
CH
+ t
CL
1 / f
C
.
2. Value guaranteed by characterization, not 100% tested in production.
3. Preliminary data: this product is under qualification. For more infomation, please contact your nearest ST sales office.
Test conditions specified in Table 11 and Table 10
Symbol
Alt.
Parameter
Min.
3
Max.
3
Unit
f
C
f
SCK
Clock Frequency
D.C.
2
MHz
t
SLCH
t
CSS1
S Active Setup Time
200
ns
t
SHCH
t
CSS2
S Not Active Setup Time
200
ns
t
SHSL
t
CS
S Deselect Time
200
ns
t
CHSH
t
CSH
S Active Hold Time
200
ns
t
CHSL
S Not Active Hold Time
200
ns
t
CH
1
t
CLH
Clock High Time
200
ns
t
CL
1
t
CLL
Clock Low Time
200
ns
t
CLCH
2
t
RC
Clock Rise Time
1
s
t
CHCL
2
t
FC
Clock Fall Time
1
s
t
DVCH
t
DSU
Data In Setup Time
40
ns
t
CHDX
t
DH
Data In Hold Time
50
ns
t
HHCH
Clock Low Hold Time after HOLD not Active
140
ns
t
HLCH
Clock Low Hold Time after HOLD Active
90
ns
t
CHHL
Clock High Set-up Time before HOLD Active
120
ns
t
CHHH
Clock High Set-up Time before HOLD not Active
120
ns
t
SHQZ
2
t
DIS
Output Disable Time
250
ns
t
CLQV
t
V
Clock Low to Output Valid
150
ns
t
CLQX
t
HO
Output Hold Time
0
ns
t
QLQH
2
t
RO
Output Rise Time
100
ns
t
QHQL
2
t
FO
Output Fall Time
100
ns
t
HHQX
2
t
LZ
HOLD High to Output Low-Z
100
ns
t
HLQZ
2
t
HZ
HOLD Low to Output High-Z
250
ns
t
W
t
WC
Write Time
10
ms
31/39
M95640, M95320
Figure 17. Serial Input Timing
Figure 18. Hold Timing
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSH
tCHSL
C
Q
AI02032
S
D
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQX
tHLQZ
M95640, M95320
32/39
Figure 19. Output Timing
C
Q
AI01449D
S
LSB OUT
D
ADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
33/39
M95640, M95320
PACKAGE MECHANICAL
Figure 20. PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
Notes: 1. Drawing is not to scale.
Table 23. PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
PDIP-B
A2
A1
A
L
b
e
D
E1
8
1
c
eA
b2
eB
E
Symb.
mm
inches
Typ.
Min.
Max.
Typ.
Min.
Max.
A
5.33
0.210
A1
0.38
0.015
A2
3.30
2.92
4.95
0.130
0.115
0.195
b
0.46
0.36
0.56
0.018
0.014
0.022
b2
1.52
1.14
1.78
0.060
0.045
0.070
c
0.25
0.20
0.36
0.010
0.008
0.014
D
9.27
9.02
10.16
0.365
0.355
0.400
E
7.87
7.62
8.26
0.310
0.300
0.325
E1
6.35
6.10
7.11
0.250
0.240
0.280
e
2.54
0.100
eA
7.62
0.300
eB
10.92
0.430
L
3.30
2.92
3.81
0.130
0.115
0.150
M95640, M95320
34/39
Figure 21. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Outline
Note: Drawing is not to scale.
Table 24. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Symb.
mm
inches
Typ.
Min.
Max.
Typ.
Min.
Max.
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
e
1.27
0.050
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
0
8
0
8
N
8
8
CP
0.10
0.004
SO-a
E
N
CP
B
e
A
D
C
L
A1
1
H
h x 45
35/39
M95640, M95320
Figure 22. TSSOP8 8 lead Thin Shrink Small Outline, Package Outline
Notes: 1. Drawing is not to scale.
Table 25. TSSOP8 8 lead Thin Shrink Small Outline, Package Mechanical Data
TSSOP8AM
1
8
CP
c
L
E
E1
D
A2
A
e
b
4
5
A1
L1
Symbol
mm
inches
Typ.
Min.
Max.
Typ.
Min.
Max.
A
1.200
0.0472
A1
0.050
0.150
0.0020
0.0059
A2
1.000
0.800
1.050
0.0394
0.0315
0.0413
b
0.190
0.300
0.0075
0.0118
c
0.090
0.200
0.0035
0.0079
CP
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
0.0256
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0.0394
0
8
0
8
M95640, M95320
36/39
Figure 23. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Outline
Notes: 1. Drawing is not to scale.
Table 26. TSSOP14 - 14 lead Thin Shrink Small Outline, Package Mechanical Data
TSSOP14-M
1
14
CP
c
L
E
E1
D
A2
A
e
b
7
8
A1
L1
Symbol
mm
inches
Typ.
Min.
Max.
Typ.
Min.
Max.
A
1.200
0.0472
A1
0.050
0.150
0.0020
0.0059
A2
1.000
0.800
1.050
0.0394
0.0315
0.0413
b
0.190
0.300
0.0075
0.0118
c
0.090
0.200
0.0035
0.0079
CP
0.100
0.0039
D
5.000
4.900
5.100
0.1969
0.1929
0.2008
e
0.650
0.0256
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.500
0.750
0.0236
0.0197
0.0295
L1
1.000
0.0394
0
8
0
8
37/39
M95640, M95320
PART NUMBERING
Table 27. Ordering Information Scheme
Note: 1. Devices bearing the process identification letter "B" or "V" in the package marking (on the top side of the package, on the right side),
guarantee more than 1 million Erase/Write cycle endurance (see Table 28, below). For more information about these devices, and
their device identification, please contact your nearest ST sales office, and ask for the Product Change Notice.
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
Table 28. How to Identify Current and Forthcoming Products by the Process Identification Letter
Note: 1. For further information, please ask your ST Sales Office for Process Change Notice PCN MPG/EE/0053 (PCEE0053) and MPG/
EE/0054 (PCEE0054).
Example:
M95320
W MN
6
T
P
Device Type
M95 = SPI serial access EEPROM
Device Function
1
640 = 64 Kbit (8192 x 8)
320 = 32 Kbit (4096 x 8)
Operating Voltage
blank = V
CC
= 4.5 to 5.5V
W = V
CC
= 2.5 to 5.5V
R = V
CC
= 1.8 to 5.5V
Package
BN = PDIP8
MN = SO8 (150 mil width)
DW = TSSOP8 (169 mil width)
DL = TSSOP14 (169 mil width)
Temperature Range
6 = 40 to 85 C
3 = 40 to 125 C
Option
blank = Standard Packing
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Pb-free plating
G = Green pack
Markings on Current Products
1
Markings on New Products
1
95640 6 (or 95640W6)
xxxxS
95640 6 (or 95640W6)
xxxxV
95640 3
xxxxS
95640 3 (or 95640W3)
xxxxB
M95640, M95320
38/39
REVISION HISTORY
Table 29. Document Revision History
Date
Rev.
Description of Revision
13-Jul-2000
1.2
Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp 1,11,15. New clause
on p7. Addition of TSSOP8 package on pp 1, 2, Ordering Info, Mechanical Data
16-Mar-2001
1.3
Test condition added I
LI
and I
LO
, and specification of t
DLDH
and t
DHDL
removed.
t
CLCH
, t
CHCL
, t
DLDH
and t
DHDL
changed to 50ns for the -V range.
"-V" Voltage range changed to "2.7V to 3.6V" throughout.
Maximum lead soldering time and temperature conditions updated.
Instruction sequence illustrations updated.
"Bus Master and Memory Devices on the SPI bus" illustration updated.
Package Mechanical data updated.
19-Jul-2001
1.4
M95160 and M95080 devices removed to their own data sheet
06-Dec-2001
1.5
Endurance increased to 1M write/erase cycles
Instruction sequence illustrations updated
18-Dec-2001
2.0
Document reformatted using the new template. No parameters changed.
08-Feb-2002
2.1
Announcement made of planned upgrade to 10 MHz clock for the 5V, 40 to 85C, range.
Endurance set to 100K write/erase cycles
18-Dec-2002
2.2
10MHz, 5MHz, 2MHz clock; 5ms, 10ms Write Time; 100K, 1M erase/write cycles distinguished
on front page, and in the DC and AC Characteristics tables
26-Mar-2003
2.3
Process indentification letter corrected in footnote to AC Characteristics table for temp. range 3
26-Jun-2003
2.4
-S voltage range upgraded by removing it and inserting -R voltage range in its place
15-Oct-2003
3.0
Table of contents, and Pb-free options added. V
IL
(min) improved to -0.45V.
21-Nov-2003
3.1
V
I
(min) and V
O
(min) corrected (improved) to -0.45V.
39/39
M95640, M95320
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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