M95160, M95080

2/40

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. DIP, SO, TSSOP and MLP Connections (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

CONNECTING TO THE SPI BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Bus Master and Memory Devices on the SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Active Power and Standby Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Data Protection and Protocol Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. Write-Protected Block Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3/40

M95160, M95080

Figure 7. Write Enable (WREN) Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. Write Disable (WRDI) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Read Status Register (RDSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Protection Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Address Range Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10.Write Status Register (WRSR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11.Read from Memory Array (READ) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12.Byte Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.Page Write (WRITE) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

POWER-UP AND DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power-up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. Operating Conditions (M95xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Operating Conditions (M95xxx-W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. Operating Conditions (M95xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 14.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 14. DC Characteristics (M95xxx, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 15. DC Characteristics (M95xxx, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 16. DC Characteristics (M95xxx-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 17. DC Characteristics (M95xxx-W, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 18. DC Characteristics (M95xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 19. AC Characteristics (M95xxx, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 20. AC Characteristics (M95xxx, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 21. AC Characteristics (M95xxx-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 22. AC Characteristics (M95xxx-W, Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 23. AC Characteristics (M95xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 15.Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 16.Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 17.Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

M95160, M95080

4/40

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 18.PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 33

Table 24. PDIP8 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 33

Figure 19.SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 34

Table 25. SO8 narrow 8 lead Plastic Small Outline, 150 mils body width, Mechanical Data . . . . 34

Figure 20.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline
35

Table 26. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data .
35

Figure 21.TSSOP8 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 36

Table 27. TSSOP8 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 36

Figure 22.TSSOP8 3x3mm² 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline
37

Table 28. TSSOP8 3x3mm² 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data
37

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 29. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 30. How to Identify Present and Previous Products by the Process Identification Letter . . . 38

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 31. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

M95160, M95080

6/40

SIGNAL DESCRIPTION

During all operations, V

must be held stable and

within the specified valid range: V

(min) to

(max).

All of the input and output signals must be held
High or Low (according to voltages of V

, V

or V

, as specified in

Table 14.

Table 18.

These signals are described next.
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be written.
Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output

(Q) is at high impedance. Unless an internal Write
cycle is in progress, the device will be in the Stand-
by Power mode. Driving Chip Select (S) Low se-
lects the device, placing it in the Active Power
mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don't Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against Write instructions (as
specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either High or Low, and
must be stable during all write instructions.

7/40

M95160, M95080

CONNECTING TO THE SPI BUS

These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output

(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.

Figure 4.

shows three devices, connected to an

MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.

Figure 4. Bus Master and Memory Devices on the SPI Bus

Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

AI03746D

Bus Master

(ST6, ST7, ST9,

ST10, Others)

SPI Memory

Device

SDO

SDI

SCK

SPI Memory

Device

SPI Memory

Device

CS3

CS2

CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

HOLD

9/40

M95160, M95080

OPERATING FEATURES

Power-up
When the power supply is turned on, V

rises

from V

to V

During this time, the Chip Select (S) must be al-
lowed to follow the V

voltage. It must not be al-

lowed to float, but should be connected to V

via

a suitable pull-up resistor.
As a built in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
Power On Reset: V

Lock-Out Write Protect

In order to prevent data corruption and inadvertent
Write instructions during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until V

has reached the Power On

Reset (POR) threshold voltage, and all operations
are disabled the device will not respond to any
instruction. In the same way, when V

drops from

the operating voltage, below the Power On Reset
(POR) threshold voltage, all operations are dis-
abled and the device will not respond to any in-
struction.

A stable and valid V

must be applied before ap-

plying any logic signal.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage applied on V

Active Power and Standby Power Modes
When Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode. The device
consumes I

, as specified in

Table 14.

Table

18.

When Chip Select (S) is High, the device is dese-
lected. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Standby
Power mode, and the device consumption drops
to I

CC1

Hold Condition
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don't Care.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the de-
vice while it is in the Hold condition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low.

The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.

M95160, M95080

10/40

Status Register

Figure 6.

shows the position of the Status Register

in the control logic of the device. The Status Reg-
ister contains a number of status and control bits
that can be read or set (as appropriate) by specific
instructions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.

Table 3. Status Register Format

Data Protection and Protocol Control
Non-volatile memory devices can be used in envi-
ronments that are particularly noisy, and within ap-
plications that could experience problems if
memory bytes are corrupted. Consequently, the

device features the following data protection
mechanisms:

Write and Write Status Register instructions
are checked that they consist of a number of
clock pulses that is a multiple of eight, before
they are accepted for execution.

All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:

Power-up

Write Disable (WRDI) instruction
completion

Write Status Register (WRSR) instruction
completion

Write (WRITE) instruction completion

The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only.
This is the Software Protected Mode (SPM).

The Write Protect (W) signal allows the Block
Protect (BP1, BP0) bits to be protected. This is
the Hardware Protected Mode (HPM).

For any instruction to be accepted, and executed,
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) for the last bit of the in-
struction, and before the next rising edge of Serial
Clock (C).
Two points need to be noted in the previous sen-
tence:

The `last bit of the instruction' can be the
eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction
(except for Read Status Register (RDSR) and
Read (READ) instructions).

The `next rising edge of Serial Clock (C)' might
(or might not) be the next bus transaction for
some other device on the SPI bus.

Table 4. Write-Protected Block Size

b7 b0

SRWD

0 0 0

BP1

BP0

WEL

WIP

Status Register Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

Status Register Bits

Protected Block

Array Addresses Protected

BP1 BP0

M95160

M95080

0 0

none

Upper quarter

0600h - 07FFh

0300h - 03FFh

Upper half

0400h - 07FFh

0200h - 03FFh

Whole memory

0000h - 07FFh

0000h - 03FFh

13/40

M95160, M95080

Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set pri-
or to each WRITE and WRSR instruction. The only
way to do this is to send a Write Enable instruction
to the device.

As shown in

Figure 7.

, to send this instruction to

the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D). The device then enters a wait
state. It waits for a the device to be deselected, by
Chip Select (S) being driven High.

Figure 7. Write Enable (WREN) Sequence

Write Disable (WRDI)
One way of resetting the Write Enable Latch
(WEL) bit is to send a Write Disable instruction to
the device.
As shown in

Figure 8.

, to send this instruction to

the device, Chip Select (S) is driven Low, and the
bits of the instruction byte are shifted in, on Serial
Data Input (D).

The device then enters a wait state. It waits for a
the device to be deselected, by Chip Select (S) be-
ing driven High.
The Write Enable Latch (WEL) bit, in fact, be-
comes reset by any of the following events:

Power-up

WRDI instruction execution

WRSR instruction completion

WRITE instruction completion.

Figure 8. Write Disable (WRDI) Sequence

AI02281E

High Impedance

Instruction

AI03750D

High Impedance

Instruction

M95160, M95080

14/40

Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Write or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register con-
tinuously, as shown in

Figure 9.

The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register in-
struction is accepted.

BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in

Table 3.

) be-

comes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.

SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) be-
come read-only bits and the Write Status Register
(WRSR) instruction is no longer accepted for exe-
cution.

Figure 9. Read Status Register (RDSR) Sequence

9 10 11 12 13 14 15

Instruction

AI02031E

Status Register Out

High Impedance

MSB

Status Register Out

MSB

15/40

M95160, M95080

Write Status Register (WRSR)
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in

Figure 10.

The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising
edge of Serial Clock (C) that latches in the eighth
bit of the data byte, and before the next rising edge
of Serial Clock (C). Otherwise, the Write Status
Register (WRSR) instruction is not executed. As
soon as Chip Select (S) is driven High, the self-
timed Write Status Register cycle (whose duration
is t

) is initiated. While the Write Status Register

cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress

(WIP) bit. The Write In Progress (WIP) bit is 1 dur-
ing the self-timed Write Status Register cycle, and
is 0 when it is completed. When the cycle is com-
pleted, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in

Table 3.

The Write Status Register (WRSR) instruction also
allows the user to set or reset the Status Register
Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected Mode (HPM). The Write Status Register
(WRSR) instruction is not executed once the Hard-
ware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable
(SRWD) and Block Protect (BP1, BP0) bits are fro-
zen at their current values from just before the
start of the execution of Write Status Register
(WRSR) instruction. The new, updated, values
take effect at the moment of completion of the ex-
ecution of Write Status Register (WRSR) instruc-
tion.

Table 6. Protection Modes

Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in

Table 6.

The protection features of the device are summa-
rized in

Table 4.

When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whether Write Protect
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the state of
Write Protect (W):

If Write Protect (W) is driven High, it is
possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write Enable
(WREN) instruction.

If Write Protect (W) is driven Low, it is not
possible to write to the Status Register even if
the Write Enable Latch (WEL) bit has
previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the
Status Register are rejected, and are not
accepted for execution). As a consequence,
all the data bytes in the memory area that are
software protected (SPM) by the Block Protect

Signal

SRWD

Bit

Mode

Write Protection of the

Status Register

Memory Content

Protected Area

Unprotected Area

Software

Protected

(SPM)

Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the BP1 and
BP0 bits can be changed

Write Protected

Ready to accept Write
instructions

Hardware
Protected

(HPM)

Status Register is
Hardware write protected
The values in the BP1 and
BP0 bits cannot be
changed

Write Protected

Ready to accept Write
instructions

17/40

M95160, M95080

Read from Memory Array (READ)
As shown in

Figure 11.

, to send this instruction to

the device, Chip Select (S) is first driven Low. The
bits of the instruction byte and address bytes are
then shifted in, on Serial Data Input (D). The ad-
dress is loaded into an internal address register,
and the byte of data at that address is shifted out,
on Serial Data Output (Q).

If Chip Select (S) continues to be driven Low, the
internal address register is automatically incre-
mented, and the byte of data at the new address is
shifted out.

When the highest address is reached, the address
counter rolls over to zero, allowing the Read cycle
to be continued indefinitely. The whole memory
can, therefore, be read with a single READ instruc-
tion.
The Read cycle is terminated by driving Chip Se-
lect (S) High. The rising edge of the Chip Select
(S) signal can occur at any time during the cycle.

The first byte addressed can be any byte within
any page.
The instruction is not accepted, and is not execut-
ed, if a Write cycle is currently in progress.

Figure 11. Read from Memory Array (READ) Sequence

Note: Depending on the memory size, as shown in

Table 7.

, the most significant address bits are Don't Care.

AI01793D

9 10

20 21 22 23 24 25 26 27

14 13

28 29 30

High Impedance

Data Out 1

Instruction

16-Bit Address

MSB

Data Out 2

M95160, M95080

18/40

Write to Memory Array (WRITE)
As shown in

Figure 12.

, to send this instruction to

the device, Chip Select (S) is first driven Low. The
bits of the instruction byte, address byte, and at
least one data byte are then shifted in, on Serial
Data Input (D).
The instruction is terminated by driving Chip Se-
lect (S) High at a byte boundary of the input data.
In the case of

Figure 12.

, this occurs after the

eighth bit of the data byte has been latched in, in-
dicating that the instruction is being used to write
a single byte. The self-timed Write cycle starts,
and continues for a period t

(as specified in

Ta-

ble 19.

Table 23.

), at the end of which the Write

in Progress (WIP) bit is reset to 0.
If, though, Chip Select (S) continues to be driven
Low, as shown in

Figure 13.

, the next byte of input

data is shifted in, so that more than a single byte,
starting from the given address towards the end of
the same page, can be written in a single internal
Write cycle.

Each time a new data byte is shifted in, the least
significant bits of the internal address counter are
incremented. If the number of data bytes sent to
the device exceeds the page boundary, the inter-
nal address counter rolls over to the beginning of
the page, and the previous data there are overwrit-
ten with the incoming data. (The page size of
these devices is 32 bytes).
The instruction is not accepted, and is not execut-
ed, under the following conditions:

if the Write Enable Latch (WEL) bit has not
been set to 1 (by executing a Write Enable
instruction just before)

if a Write cycle is already in progress

if the device has not been deselected, by Chip
Select (S) being driven High, at a byte
boundary (after the eighth bit, b0, of the last
data byte that has been latched in)

if the addressed page is in the region
protected by the Block Protect (BP1 and BP0)
bits.

Figure 12. Byte Write (WRITE) Sequence

Note: Depending on the memory size, as shown in

Table 7.

, the most significant address bits are Don't Care.

AI01795D

9 10

20 21 22 23 24 25 26 27

14 13

28 29 30

High Impedance

Instruction

16-Bit Address

Data Byte

21/40

M95160, M95080

MAXIMUM RATING

Stressing the device outside the ratings listed in

Table 8.

may cause permanent damage to the de-

vice. These are stress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of

this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to
the STMicroelectronics SURE Program and other
relevant quality documents.

Table 8. Absolute Maximum Ratings

Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK

7191395 specification, and

the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU

2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500

, R2=500

)

Symbol

Parameter

Min.

Max.

Unit

STG

Storage Temperature

150

°C

LEAD

Lead Temperature during Soldering

See note

°C

Output Voltage

0.50

+0.6

Input Voltage

0.50

6.5

Supply Voltage

0.50

6.5

ESD

Electrostatic Discharge Voltage (Human Body model)

4000

M95160, M95080

22/40

DC AND AC PARAMETERS

This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-

ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.

Table 9. Operating Conditions (M95xxx)

Table 10. Operating Conditions (M95xxx-W)

Table 11. Operating Conditions (M95xxx-R)

Note: 1. This product is under development. For more information, please contact your nearest ST sales office.

Table 12. AC Measurement Conditions

Note: Output Hi-Z is defined as the point where data out is no longer driven.

Figure 14. AC Measurement I/O Waveform

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

4.5

5.5

Ambient Operating Temperature (Device Grade 6)

°C

Ambient Operating Temperature (Device Grade 3)

125

°C

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

2.5

5.5

Ambient Operating Temperature (Device Grade 6)

°C

Ambient Operating Temperature (Device Grade 3)

125

°C

Symbol

Parameter

Min.

Max.

Unit

Supply Voltage

1.8

5.5

Ambient Operating Temperature

°C

Symbol

Parameter

Min.

Max.

Unit

Load Capacitance

100

Input Rise and Fall Times

Input Pulse Voltages

0.2V

to 0.8V

Input and Output Timing Reference Voltages

0.3V

to 0.7V

AI00825B

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

23/40

M95160, M95080

Table 13. Capacitance

Note: Sampled only, not 100% tested, at T

=25°C and a frequency of 5 MHz.

Table 14. DC Characteristics (M95xxx, Device Grade 6)

Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.

2. Previous product: identified by Process Identification letter L.
3. Present product: identified by Process Identification letter W or G.

Symbol

Parameter

Test Condition

Min.

Max.

Unit

OUT

Output Capacitance (Q)

OUT

= 0V

Input Capacitance (D)

= 0V

Input Capacitance (other pins)

= 0V

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

= V

± 2

µA

Output Leakage Current

S = V

, V

OUT

= V

± 2

µA

Supply Current

C = 0.1V

/0.9V

at 5MHz,

= 5 V, Q = open, Previous Product

C = 0.1V

/0.9V

at 10MHz,

= 5 V, Q = open, Present Product

CC1

Supply Current
(Standby Power mode)

S = V

, V

= 5 V,

= V

, Previous Product

µA

S = V

, V

= 5 V,

= V

, Present Product

µA

Input Low Voltage

0.45

0.3 V

Input High Voltage

0.7 V

Output Low Voltage

= 2 mA, V

= 5 V

0.4

Output High Voltage

= 2 mA, V

= 5 V

0.8 V

M95160, M95080

24/40

Table 15. DC Characteristics (M95xxx, Device Grade 3)

Note: 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards.

2. Previous product: identified by Process Identification letter L.
3. Present product: identified by Process Identification letter W or G.

Table 16. DC Characteristics (M95xxx-W, Device Grade 6)

Note: 1. Previous product: identified by Process Identification letter L.

2. Present product: identified by Process Identification letter W or G.

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

= V

± 2

µA

Output Leakage Current

S = V

, V

OUT

= V

± 2

µA

Supply Current

C = 0.1V

/0.9V

at 2 MHz,

= 5 V, Q = open, Previous Product

C = 0.1V

/0.9V

at 5 MHz,

= 5 V, Q = open, Present Product

CC1

Supply Current
(Standby Power mode)

S = V

, V

= 5 V,

= V

, Previous Product

µA

S = V

, V

= 5 V,

= V

, Present Product

µA

Input Low Voltage

0.45

0.3 V

Input High Voltage

0.7 V

Output Low Voltage

= 2 mA, V

= 5 V

0.4

Output High Voltage

= 2 mA, V

= 5 V

0.8 V

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

= V

± 2

µA

Output Leakage Current

S = V

, V

OUT

= V

± 2

µA

Supply Current

C = 0.1V

/0.9V

at 2 MHz,

= 2.5 V, Q = open, Previous Product

C = 0.1V

/0.9V

at 5 MHz,

= 2.5 V, Q = open, Present Product

CC1

Supply Current
(Standby Power mode)

S = V

, V

= 2.5 V,

= V

, Previous Product

µA

S = V

, V

= 2.5 V

= V

, Present Product

µA

Input Low Voltage

0.45

0.3 V

Input High Voltage

0.7 V

Output Low Voltage

= 1.5 mA, V

= 2.5 V

0.4

Output High Voltage

= 0.4 mA, V

= 2.5 V

0.8 V

25/40

M95160, M95080

Table 17. DC Characteristics (M95xxx-W, Device Grade 3)

Note: 1. Previous product: identified by Process Identification letter L.

2. Present product: identified by Process Identification letter W or G.

Table 18. DC Characteristics (M95xxx-R)

Note: 1. This product is under development. For more information, please contact your nearest ST sales office.

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

= V

± 2

µA

Output Leakage Current

S = V

, V

OUT

= V

± 2

µA

Supply Current

C = 0.1V

/0.9V

at 2 MHz,

= 2.5 V, Q = open, Previous Product

C = 0.1V

/0.9V

at 5 MHz,

= 2.5 V, Q = open, Present Product

CC1

Supply Current
(Standby Power mode)

S = V

, V

= 2.5 V, V

= V

µA

Input Low Voltage

0.45

0.3 V

Input High Voltage

0.7 V

Output Low Voltage

= 1.5 mA, V

= 2.5 V

0.4

Output High Voltage

= 0.4 mA, V

= 2.5 V

0.8 V

Symbol

Parameter

Test Condition

Min.

Max.

Unit

Input Leakage Current

= V

± 2

µA

Output Leakage Current

S = V

, V

OUT

= V

± 2

µA

Supply Current

C = 0.1V

/0.9V

at 2 MHz,

= 1.8 V, Q = open

CC1

Supply Current
(Standby Power mode)

S = V

, V

= V

, V

= 1.8 V

0.5

µA

Input Low Voltage

0.45

0.3 V

Input High Voltage

0.7 V

Output Low Voltage

= 0.15 mA, V

= 1.8 V

0.3

Output High Voltage

= 0.1 mA, V

= 1.8 V

0.8 V

M95160, M95080

26/40

Table 19. AC Characteristics (M95xxx, Device Grade 6)

Note: 1. t

+ t

must never be less than the shortest possible clock period, 1 / f

(max)

2. Value guaranteed by characterization, not 100% tested in production.
3. To be characterized.
4. Previous product: identified by Process Identification letter L.
5. Present product: identified by Process Identification letter W or G.

Test conditions specified in

Table 12.

and

Table 9.

Symbol

Alt.

Parameter

Min.

Max.

Min.

Max.

Unit

SCK

Clock Frequency

D.C.

MHz

SLCH

CSS1

S Active Setup Time

SHCH

CSS2

S Not Active Setup Time

SHSL

S Deselect Time

100

CHSH

CSH

S Active Hold Time

CHSL

S Not Active Hold Time

CLH

Clock High Time

CLL

Clock Low Time

CLCH

Clock Rise Time

µs

CHCL

Clock Fall Time

µs

DVCH

DSU

Data In Setup Time

CHDX

Data In Hold Time

HHCH

Clock Low Hold Time after HOLD not Active

HLCH

Clock Low Hold Time after HOLD Active

CLHL

Clock Low Set-up Time before HOLD Active

CLHH

Clock Low Set-up Time before HOLD not Active

SHQZ

DIS

Output Disable Time

100

CLQV

Clock Low to Output Valid

CLQX

Output Hold Time

QLQH

Output Rise Time

QHQL

Output Fall Time

HHQV

HOLD High to Output Valid

HLQZ

HOLD Low to Output High-Z

100

Write Time

27/40

M95160, M95080

Table 20. AC Characteristics (M95xxx, Device Grade 3)

Note: 1. t

+ t

must never be less than the shortest possible clock period, 1 / f

(max)

Test conditions specified in

Table 12.

and

Table 9.

Symbol

Alt.

Parameter

Min.

Max.

Min.

Max.

Unit

SCK

Clock Frequency

D.C.

MHz

SLCH

CSS1

S Active Setup Time

200

SHCH

CSS2

S Not Active Setup Time

200

SHSL

S Deselect Time

200

100

CHSH

CSH

S Active Hold Time

200

CHSL

S Not Active Hold Time

200

CLH

Clock High Time

200

CLL

Clock Low Time

200

CLCH

Clock Rise Time

µs

CHCL

Clock Fall Time

µs

DVCH

DSU

Data In Setup Time

CHDX

Data In Hold Time

HHCH

Clock Low Hold Time after HOLD not Active

140

HLCH

Clock Low Hold Time after HOLD Active

CLHL

Clock Low Set-up Time before HOLD Active

CLHH

Clock Low Set-up Time before HOLD not
Active

SHQZ

DIS

Output Disable Time

250

100

CLQV

Clock Low to Output Valid

150

CLQX

Output Hold Time

QLQH

Output Rise Time

100

QHQL

Output Fall Time

100

HHQV

HOLD High to Output Valid

100

HLQZ

HOLD Low to Output High-Z

250

100

Write Time

M95160, M95080

28/40

Table 21. AC Characteristics (M95xxx-W, Device Grade 6)

Note: 1. t

+ t

must never be less than the shortest possible clock period, 1 / f

(max)

Test conditions specified in

Table 12.

and

Table 10.

Symbol

Alt.

Parameter

Min.

Max.

Min.

Max.

Unit

SCK

Clock Frequency

D.C.

MHz

SLCH

CSS1

S Active Setup Time

200

SHCH

CSS2

S Not Active Setup Time

200

SHSL

S Deselect Time

200

100

CHSH

CSH

S Active Hold Time

200

CHSL

S Not Active Hold Time

200

CLH

Clock High Time

200

CLL

Clock Low Time

200

CLCH

Clock Rise Time

µs

CHCL

Clock Fall Time

µs

DVCH

DSU

Data In Setup Time

CHDX

Data In Hold Time

HHCH

Clock Low Hold Time after HOLD not Active

140

HLCH

Clock Low Hold Time after HOLD Active

CLHL

Clock Low Set-up Time before HOLD Active

CLHH

Clock Low Set-up Time before HOLD not Active

SHQZ

DIS

Output Disable Time

250

100

CLQV

Clock Low to Output Valid

150

CLQX

Output Hold Time

QLQH

Output Rise Time

100

QHQL

Output Fall Time

100

HHQV

HOLD High to Output Valid

100

HLQZ

HOLD Low to Output High-Z

250

100

Write Time

29/40

M95160, M95080

Table 22. AC Characteristics (M95xxx-W, Device Grade 3)

Note: 1. t

+ t

must never be less than the shortest possible clock period, 1 / f

(max)

Test conditions specified in

Table 12.

and

Table 10.

Symbol

Alt.

Parameter

Min.

Max.

Min.

Max.

Unit

SCK

Clock Frequency

D.C.

MHz

SLCH

CSS1

S Active Setup Time

200

SHCH

CSS2

S Not Active Setup Time

200

SHSL

S Deselect Time

200

100

CHSH

CSH

S Active Hold Time

200

CHSL

S Not Active Hold Time

200

CLH

Clock High Time

200

CLL

Clock Low Time

200

CLCH

Clock Rise Time

µs

CHCL

Clock Fall Time

µs

DVCH

DSU

Data In Setup Time

CHDX

Data In Hold Time

HHCH

Clock Low Hold Time after HOLD not Active

140

HLCH

Clock Low Hold Time after HOLD Active

CLHL

Clock Low Set-up Time before HOLD Active

CLHH

Clock Low Set-up Time before HOLD not
Active

SHQZ

DIS

Output Disable Time

250

100

CLQV

Clock Low to Output Valid

150

CLQX

Output Hold Time

QLQH

Output Rise Time

100

QHQL

Output Fall Time

100

HHQV

HOLD High to Output Valid

100

HLQZ

HOLD Low to Output High-Z

250

100

Write Time

M95160, M95080

30/40

Table 23. AC Characteristics (M95xxx-R)

Note: 1. t

+ t

must never be less than the shortest possible clock period, 1 / f

(max)

2. Value guaranteed by characterization, not 100% tested in production.
3. To be characterized.
4. This product is under development. For more information, please contact your nearest ST sales office.
5. This is preliminary data.

Test conditions specified in

Table 12.

and

Table 11.

Symbol

Alt.

Parameter

Min.

4,5

Max.

4,5

Unit

SCK

Clock Frequency

D.C.

MHz

SLCH

CSS1

S Active Setup Time

200

SHCH

CSS2

S Not Active Setup Time

200

SHSL

S Deselect Time

200

CHSH

CSH

S Active Hold Time

200

CHSL

S Not Active Hold Time

200

CLH

Clock High Time

200

CLL

Clock Low Time

200

CLCH

Clock Rise Time

µs

CHCL

Clock Fall Time

µs

DVCH

DSU

Data In Setup Time

CHDX

Data In Hold Time

HHCH

Clock Low Hold Time after HOLD not Active

140

HLCH

Clock Low Hold Time after HOLD Active

CLHL

Clock Low Set-up Time before HOLD Active

CLHH

Clock Low Set-up Time before HOLD not Active

SHQZ

DIS

Output Disable Time

250

CLQV

Clock Low to Output Valid

150

CLQX

Output Hold Time

QLQH

Output Rise Time

100

QHQL

Output Fall Time

100

HHQV

HOLD High to Output Valid

100

HLQZ

HOLD Low to Output High-Z

250

Write Time

M95160, M95080

38/40

PART NUMBERING

Table 29. Ordering Information Scheme

Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-

tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.

2. TSSOP8, 169 mil width, package is not available for the M95160 identified by the process identification letter L.
3. TSSOP8, 3x3mm body size, package is available for the M95080 series only.
4. Used only for Device Grade 3

For a list of available options (speed, package,
etc.) or for further information on any aspect of this

device, please contact your nearest ST Sales Of-
fice.

Table 30. How to Identify Present and Previous Products by the Process Identification Letter

Note: 1. This example comes from the S08 package. Other packages have similar information. For further information, please ask your ST

Sales Office for Process Change Notice PCN MPG/EE/0034 (PCEE0034).

Example:

M95160

W MN

Device Type
M95 = SPI serial access EEPROM

Device Function
160 = 16 Kbit (2048 x 8)
080 = 8 Kbit (1024 x 8)

Operating Voltage
blank = V

= 4.5 to 5.5V

W = V

= 2.5 to 5.5V

R = V

= 1.8 to 5.5V

Package
BN = PDIP8
MN = SO8 (150 mil width)

= TSSOP8

= TSSOP8 (3x3mm body size, MSOP)

MB = MLP8 (UFDFPN8)

Device Grade
6 = Industrial temperature range, 40 to 85 °C.
Device tested with standard test flow

3 = Device tested with High Reliability Certified Flow

Automotive temperature range (40 to 125 °C)

Option
blank = Standard Packing
T = Tape and Reel Packing

Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb

-free and TBBA-free

Process

blank = F6SP20%
/W = F6SP36%

Markings on Present Products

Markings on Previous Products

95160W6

AYWWW (or AYWWG)

95160W6

AYWWL

39/40

M95160, M95080

REVISION HISTORY

Table 31. Document Revision History

Date

Rev.

Description of Revision

19-Jul-2001

1.0

Document written from previous M95640/320/160/080 datasheet

06-Feb-2002

1.1

Announcement made of planned upgrade to 10MHz clock for the 5V, 40 to 85°C, range

18-Oct-2002

1.2

TSSOP8 (3x3mm body size, MSOP8) package added

04-Nov-2002

1.3

New products, identified by the process letter W, added

13-Nov-2002

1.4

Correction to footnote in Ordering Information table

21-Nov-2003

2.0

Table of contents, and Pb-free options added. V

(min) improved to 0.45V

08-Jun-2004

3.0

MLP8 package added. Absolute Maximum Ratings for V

(min) and V

(min) improved.

Soldering temperature information clarified for RoHS compliant devices. Device Grade 3
clarified, with reference to HRCF and automotive environments. Process identification letter
"G" information added. SO8 narrow and TSSOP8 Package mechanical specifications updated.

07-Oct-2004

4.0

Product List summary table added. AEC-Q100-002 compliance. tHHQX corrected to tHHQV.
10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint clarified

M95160, M95080

40/40

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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M95080-WBN6

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: M95080-WBN6