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MTC20136
February 2004
Dedicated controller for use with ADSL
transceiver chips MTC20134, MTC20135 and
MTC20455
Performs ADSL control functions :
Initialization procedure
Line monitoring during operation
Rate adaptive modes
Supports the modem control interface protocol
(CTRLE)
Embedded high speed ARM microcore
Glueless connection to MTC20135 and
MTC20455
Parallel or serial modem control interface
(CTRLE) for glueless connection to
management entities
Embedded UART
Supports code download
External Bus Interface for 8 and 16-bit FEPROM
and 16-bit SDRAM
144 pins PQFP
DESCRIPTION
The MTC20136 is a dedicated controller chip, spe-
cifically designed to control operations of the ST-
Microelectronics DynaMiTe chipset. The
MTC20136 offers direct glueless interfaces to the
MTC20135 and MTC20455 DMT/ATM transciever
and implements a complete control interface for
parameters and commands exchange between
transceiver and system management. All real time
ADSL-related functions (including EOC process-
ing) are completely handled by the MTC20136.
PQFP144
LFBGA160
ORDERING NUMBERS:
Part number
Package
Temp.
MTC20136PQ- l1
144 pin PQFP
-40 /+85C
MTC20136MB-I1
160 pin LBGA
-40 /+85C
Can also be ordered using kit number MTK20131 or
MTC20455
ADSL TRANSCEIVER CONTROLLER
Figure 1. Block Diagram
ARM
Microcore
ROM
RAM
TIMER
CTRLE Data
buffer
Peripherals
CTRLE
Microcontroller
Interface
Logic
RS232
General
Purpose I/Os
Control Bus
8 data
9 address
External Bus
Interface
Local Bus
MTC20136
FEPROM
(optional)
SDRAM
MTC-20135
or
MTC-20455
UART
Parallel
I/O
MTC20136
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Functional Description
Figure 1 is showing the global block diagram of the MTC20136. The functions can be grouped into the
following:
Microcontroller
External Bus Interface
Control Interface (CTRLE)
Peripherals
Miscellaneous
Microcontroller
The microcontroller block includes an ARM-based microcore and its associated internal memory. 16
Kbytes on internal RAM and 128 x 32-bit words of ROM are foreseen. The ROM essentially contains the
boot sequence needed for code download at startup. The use of the ROM by the microcore is defined by
the state of the TROM pin during reset.
External Bus Interface
The External Bus Interface extends the internal microcontroller bus for connection of external devices. In
particular, the bus is used to connect to the MTC20135 or MTC20455 modem chip and to external SDRAM
(and optional FEEPROM).
The CTRLE functional block implements the ADSL modem command and data buffer and the interface
logic supporting the physical interfaces of the CTRLE.
Peripherals
The peripherals block includes two UARTS for RS232 interfacing to external systems and two general =
purpose parallel I/O lines.
Miscellaneous
This includes the clock circuitry, reset circuitry, test functions and configuration control signals.
CTRLE Interfaces
External Bus Interface
The external bus interface (EBI) provides a glueless interface to 8 and 16-bit asynchronous Flash EE-
PROM, 16 bit SDRAM devices and to slave devices with an i960-like 16 bit bus interface with multiplexed
address and data (as available on DynaMiTe chips).
The EBI provides two chip selects (E_nCS[1:0]) to be used for memory access (SRAM-like), one dedicat-
ed SDRAM chip select ((E_nCS_S) and four chip selects (E_nCS[7:4]) to be used for access to ADSL
slave devices. The chip selects all correspond to a fixed 1Mbyte memory region in the microcontroller
memory map, except for SDRAM access.
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MTC20136
PIN LAYOUT
Functional Pin Summary
The signals hereunder are grouped per functional interface.
Figure 2. Pin functional description and type per interface
Test Interface
JTAG Interface
Peripherals
EBI Interface
CTRL-E Interface
Misc
NTRST
TCK
TDI
TMS
IDDQ
T_REQA
T_REQB
C_clk
C_A[8:0]
C_notCS
C_Mode[1:0]
C_notWr
C_notRd
TROM
EIT[3:0]
notCS[7:0]
E_A[19:16]
E_A[15:0]
E_D[15:0]
CLK_E
RESETN
RSRXD2
RSTXD2
TDO
T_ACK
E_CLK
E_ALE
E_nRDY
E_nWEO
E_nWE1
C_D[7:0]
C_notint
C_notRdy
Boot_M[1:0]
RSRXD1
RSTXD1
PA1
PA0
MTC20136
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The table below describes the pins, organized per interface. Some of these pins have a multiple function-
ality. In this case both functionalities are mentioned.
Name
I/O Type
Description
External Bus Interface
E_A[19:16]
O
Address bus MSBs
E_A[15:0]
I/O
Address bus LSBs / Testbus MSBs
E_D[15:0]
I/O
Data bus / Testbus LSBs
E_CLK
O
EBI clock (ASIC Access)
E_ALE
O
Address latch enable (ASIC Access)
E_nCS_0
O
Chip select signal (Memory Bank 0)
E_nCS_1
O
Chip select signal (Memory Bank 1)
E_nCS_S
O
Chip select signal (SDRAM)
E_nCS_4
O
Chip select signal (ASIC 1)
E_nCS_5
O
Chip select signal (ASIC 2)
E_nCS_6
O
Chip select signal (ASIC 3)
E_nCS_7
O
Chip select signal (ASIC 4)
E_nRDYRCV
I
Data acknowledge
E_nOE
O
Output enable
E_nWE0
O
Write enable LSB / W/notR indication
E_nWE1
O
Write enable MSB
Clock Bus Interface
CLK_IN
I
MTC20136 Master clock
Parallel Port Interface
PA[0]
I/O
Port A bit[0]
PA[1]
I/O
Port A bit[1]
UART1 Interface
RSTXD1
O
Serial TX port
RSRXD1
I
Serial RX port
UART2 Interface
RSTXD2
O
Serial TX port
RSRXD2
I
Serial RX port
Interrupt Interface
EIT_0
I
External interrupt lines
EIT_1
I
External interrupt lines
EIT_2
I
External interrupt lines
EIT_3
I
External interrupt lines
JTAG Interface
nTRST
I-PU
Reset JTAG interface
TCK
I-PU
JTAG clock
TDI
I-PU
Test Data In
TMS
I-PU
Test Mode Select
TDO
O
Test Data Out
Reset Interface
RESETN
I
Reset signal (Active High)
Boot Interface
TROM
I
Boot from ROM select
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MTC20136
Boot_M0
I/O
Download Mode .UART BaudRate.
(Auto adjust or 9600 Bps).
Boot_M1
I/O
Download Mode Select (CTRL-E or UART1)
Ctrl-E Interface (Parallel mode only described - see above for Serial Mode)
C_A[8:0]
I
Address bus (5 V tolerant)
C_D[7:0]
IO
Data bus (5 V tolerant)
C_nCS
I
Chip select (5 V tolerant)
C_nInt
OD
Ctrl-E external interrupt
C_mode[1:0]
I
Ctrl-E interface bus mode (5 V tolerant)
C_nWr
I
Write indication (5V tolerant)
C_nRd
I
Read indication (5V tolerant)
C_nRdy
OZ
Ready indication
C_clk
I
Serial Input clock (5V tolerant)
I
=
Input, CMOS levels
I-PU
=
Input with pull-up resistance, CMOS levels
I-PD
=
Input with pull-down resistance, CMOS levels
I-TTL
=
Input TTL levels
O
=
Push-pull output
OZ
=
Push-pull output with high-impedance state
OD
=
Open Drain output
IO
=
input / Tri-state Push-pull output
PQFP144 Pin Configuration
(Default Value between ( ))
Pin#
Name
Function
1
E_A14
EBI Address
2
E_A15
EBI Address
3
E_A16
EBI Address
4
E_A17
EBI Address
5
VDD
VDD
6
VSS
VSS
7
E_A18
EBI Address
8
E_A19
EBI Address
9
EIT0
External Interrupt In - 0
10
EIT1
External Interrupt In - 1
11
VDD
VDD
12
VSS
VSS
13
EIT2
External Interrupt In - 2
14
EIT3
External Interrupt In -3
15
I_MODE
Tracking ICE Mode Select (0)
16
E_CLK
EBI Clock Out
17
E_ALE
EBI ALE
18
VDD
VDD
Name
I/O Type
Description
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