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MTC20454
February 2004
Fully integrated quad AFE for ADSL
Overall 12 bit resolution
1.1MHz signal bandwidth
8.8 MS/s ADC
8.8 MS/s DAC
THD: -60 dB @ full scale
1 V full scale input
Differential analog I/O
Accurate continuous-time channel filtering
3rd & 4th order tuneable continuous time LP
Filters
100 pin TQFP package, Industrial Range
qualified
175 mW power consumption per line
APPLICATIONS
ADSL Front-end for high density, low power
central office and digital loop carrier equipment
DESCRIPTION
The MTC20454 is the first DynaMiTe ADSL (Asyn-
chronous Digital Subscriber Line) analog front end
designed specifically for the central office. It is a
fifth generation Analog Front End (AFE) designed
for DMT based ADSL modems compliant with ITU
G.992.1 and G.992.1 standards. It includes four 12
bit DACs and one 13 bit ADC.
It is intended to be used with the MTC20455 DMT/
ATM processor as part of the MTK20450. The
MTC20454 provides programmable low pass fil-
ters for each of the two channels and automatic
gain control for four individual ADSL modems.
The pipeline ADC architecture provides 13 bit dy-
namic range and a signal bandwidth of 1.1 MHz.
The device consumes only 0.7 Watt in full opera-
tion of all four modems and has a power down
mode for standby.
It is housed in a compact 100 pin thin plastic quad
flat package.
TQFP100 14x14x1.4
ORDERING NUMBER: MTC20454-TQ-I
QUAD INTEGRATED ADSL CMOS
ANALOG FRONT END CIRCUIT
Figure 1. Sample board layout
ATM
SDRAM
MTC20136
Modem
Controller
Line
Discrete
FE
MTC20454
Quad Analog Front End
MTC20455
Quad ADSL DMT Modem
and ATM Framer
LD
LD
LD
LD
Discrete
FE
Discrete
FE
Discrete
FE
MTC20454
2/15
PIN DESCRIPTION
N
Pin
Description
Connection
Type
Digital Interface
1
DVSS
Negative supply for input IOs + core
Dig supply
VSSI
2
TX7
Transmit data bus bit 7 (MSB)
MTC-20455
SCHMITTC
3
TX6
Transmit data bus bit 6
MTC-20455
SCHMITTC
4
TX5
Transmit data bus bit 5
MTC-20455
SCHMITTC
5
TX4
Transmit data bus bit 4
MTC-20455
SCHMITTC
6
TX3
Transmit data bus bit 3
MTC-20455
SCHMITTC
7
TX2
Transmit data bus bit 2
MTC-20455
SCHMITTC
8
TX1
Transmit data bus bit 1
MTC-20455
SCHMITTC
9
TX0
Transmit data bus bit 0 (LSB)
MTC-20455
SCHMITTC
10
CTRLIN
Serial control interface input
MTC-20455
SCHMITTC
11
CLKIN
Master clock (35.328MHz) input
System
SCHMITTC
12
DVDD
Positive supply for input IOs + core
Dig supply
VDDI
13
DVDD
Positive supply for output IOs
Dig supply
VDDE
14
CLKM
Master clock output
System
BD4SCR
15
CLKWD
Word clock output
System
BT4CR
16
RX3
Receive data bus bit 3 (MSB)
MTC-20455
BT4CR
17
RX2
Receive data bus bit 2
MTC-20455
BT4CR
18
RX1
Receive data bus bit 1
MTC-20455
BT4CR
19
RX0
Receive data bus bit 0 (LSB)
MTC-20455
BT4CR
20
DVSS
Negative supply for output IOs
Dig supply
VSSE
98
ONELINE
If high: TX, RX itfce is MTC-20455 compatible System
SCHMITTC
99
RESETN
General reset (active low)
System
SCHMITTC
100
TEST
Test mode selection (static)
Strap
SCHMITTC
Analog Interface
21
AVSSADC
ADC analog negative supply
Ana supply
VSSI
25
AVDDADC
ADC analog positive supply
Ana supply
VDDI
28
VREF
ADC virtual ground decoupling
C network
OANA
29
VRAN
ADC negative reference decoupling
C network
OANA
30
VRAP
ADC positive reference decoupling
C network
OANA
32
DACVREF
DAC's voltage reference decoupling
C network
OANA
34
L3GP0
Analog general purpose control pin - Line3
Board
BT4CR
35
AVDDDAC
DAC's analog positive supply
Ana supply
VDDI
37
L3GP1
Analog general purpose control pin - Line3
Board
BT4CR
38
L2GP0
Analog general purpose control pin - Line2
Board
BT4CR
39
L2GP1
Analog general purpose control pin - Line2
Board
BT4CR
40
AVSSDAC
DAC's analog negative supply
Ana supply
VSSI
41
AVSSDS
DS filters analog negative supply
Ana supply
VSSI
42
L3DRVSD
External TX driver shutdown - Line3
TX driver
BT4CR
43
AVDDDS
DS filters analog positive supply
Ana supply
VSSI
44
AVDD TXDRV
Internal TX pre-drivers positive supply
Ana supply
VDDI
45
L3DRV0
External TX driver bias control LSB - Line3
TX driver
BT4CR
46
AVSS TXDRV
Internal pre-drivers negative supply
Ana supply
VSSI
47
L3DRV1
External TX driver bias control MSB - Line3
TX driver
BT4CR
48
L2DRVSD
External TX driver shutdown - Line2
TX driver
BT4CR
49
L2DRV0
External TX driver bias control LSB - Line2
TX driver
BT4CR
50
L2DRV1
External TX driver bias control MSB - Line2
TX driver
BT4CR
3/15
MTC20454
N
Pin
Description
Connection
Type
51
L3AVSSLNA
LNA analog negative supply - Line3
Ana suppply
VSSI
52
L3RXN
Analog RX signal negative input (diff) - Line3
RX input
OANA
53
L3RXP
Analog RX signal positive input (diff) - Line3
RX input
OANA
54
L3AVDDLNA
LNA analog positive supply - Line3
Ana supply
VDDI
55
L3TXN
Analog TX signal negative output (diff) - Line3 TX output
OANA
56
L3TXP
Analog TX signal positive output (diff) - Line3
TX output
OANA
57
L2AVSSLNA
LNA analog negative supply - Line2
Ana supply
VSSI
58
L2RXN
Analog RX signal negative input (diff) - Line 2
RX input
OANA
59
L2RXP
Analog RX signal positive input (diff) - Line2
RX input
OANA
60
L2AVDDLNA
LNA analog positive supply - Line 2
Ana supply
VDDI
61
L2TXN
Analog TX signal negative output (diff) - Line2 TX output
OANA
62
L2TXP
Analog TX signal positive output (diff) - Line2
TX output
OANA
63
L1AVSSLNA
LNA analog negative supply - Line1
Ana supply
VSSI
64
L1RXN
Analog RX signal negative input (diff) - Line1
RX input
OANA
65
L1RXP
Analog RX signal positive input (diff) - Line1
RX input
OANA
66
L1AVDDLNA
LNA analog positive supply - Line1
Ana supply
VDDI
67
L1TXN
Analog TX signal negative output (diff) - Line1 TX output
OANA
68
L1TXP
Analog TX signal positive output (diff) - Line1
TX output
OANA
69
L0AVSSLNA
LNA analog negative supply - Line0
Ana supply
VSSI
70
L0RXN
Analog RX signal negative input (diff) - Line0
RX input
OANA
71
L0RXP
Analog RX signal positive input (diff) - Line0
RX input
OANA
72
L0AVDDLNA
LNA analog positive supply - Line0
Ana supply
VDDI
73
L0TXN
Analog TX signal negative output (diff) - Line0 TX output
OANA
74
L0TXP
Analog TX signal positive output (diff) - Line0
TX output
OANA
75
VAGND
Analog virtual ground
C network
OANA
76
L1DRVSD
External TX driver shutdown - Line1
TX driver
BT4CR
77
L1DRV1
External TX driver bias control MSB - Line1
TX driver
BT4CR
78
L1DRV0
External TX driver bias control LSB - Line1
TX driver
BT4CR
79
L0DRVSD
External TX driver shutdown - Line0
TX driver
BT4CR
80
AVSS TXDRV
Internal pre-drivers negative supply
Ana supply
VSS
81
L0DRV1
External TX driver bias control MSB - Line0
TX driver
BT4CR
82
AVDD TXDRV
Internal TX pre-drivers positive supply
Ana supply
VDDI
83
AVDDDS
DS filters analog positive supply
Ana supply
VSSI
84
L0DRV0
External TX driver bias control LSB - Line0
TX driver
BT4CR
85
AVSSDS
DS filters analog negative supply
Ana supply
VSSI
86
AVSSDAC
DAC's analog negative supply
Ana supply
VSSI
89
L1GP0
Analog general purpose control pin - Line1
Board
BT4CR
90
L1GP1
Analog general purpose control pin - Line1
Board
BT4CR
91
AVDDDAC
DAC analog positive supply
Ana supply
VDDI
92
L0GP0
Analog general purpose control pin - Line0
Board
BT4CR
93
L0GP1
Analog general purpose control pin - Line0
Board
BT4CR
Analog Test Access Interface
87
TOP
Pos. diff. output test access
Test
Analog
88
TON
Neg. diff output test access
Test
Analog
94
TIN
Pos. diff input test access
Test
Analog
95
TIP
Neg. diff inp0ut test access
Test
Analog
PIN DESCRIPTION (continued)
MTC20454
4/15
Figure 2. MTC20454 Grounding and Decoupling Networks
Figure 3. PIN CONNECTION
Analog VDD
10
F
100nF
A VDD
(each pin must have
its own capacitor)
VRAP pin
VREP pin
VRAN pin
100nF
100nF
100nF
100nF
10F
10
F
DACVREF pin
100nF
AGND pin
100nF
10
F
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TEST
RESETN
ONELINE
TIP
TIN
LOGP1
LOGP0
AVDDAC
LAGP1
LAGP0
TON
TOP
AVSSDAC
AVSSDS
LODR
V0
AVDDDS
AVDDTXDR
V
LODR
V1
AVSSTXDR
V
LODR
VSD
LIDR
V0
LIDR
V1
LIDR
VSD
VREF
VRAN
VRAP
DACVREF
L3GP0
A
VDDDAC
L3GP1
L2GP0
L2GP1
A
VSSDAC
A
VSSDS
L3DR
VSD
A
VDDDS
A
VDDTXDR
V
L3DR
V0
A
VSSTXDR
V
L3DR
V1
L2DR
VSD
L3DR
V0
L2DR
V1
L3A
VSSLNA
L3RXN
L3RXP
L3A
VDDLNA
L3A
VDDLNA
L3TXN
L3TXP
L2A
VSSLNA
L2RXN
L2RXP
L2A
VDDLNA
L2TXN
L2TXP
L1A
VSSLNA
L1RXN
LIRXP
LIA
VDDLNA
LITXN
LITXP
LOA
VSSLNA
LORXN
LDRXP
LOA
VDDLNA
LOTXN
LOTXP
V
AGND
A
VDDADC
A
VSSADC
DVSS
RX0
RX1
RX2
RX3
CLKWD
CLKM
DVDD
DVDD
CLKIN
CTRLIN
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
DVSS
5/15
MTC20454
ABSOLUTE MAXIMUM RATINGS
Operation of the device beyond these limits may cause permanent damage. It is not implied that more than
one of these conditions can be applied simultaneously.
OPERATING CONDITIONS
Unless specified, the characteristic limits of `Static characteristics' in this document apply for the following
operating conditions:
ELECTRICAL CHARACTERISTICS
Static Characteristics
a. Digital Inputs
Schmitt-trigger inputs: TXi, CTRLIN, CLKIN, RESETN, TEST
Clock Driver Input
b. Digital Outputs
Hard driven outputs: RXi, CLKWD, LiGPi, LiDRVi, LiDRVSD
Clock Driver Output
Symbol
Parameter Description
Min
Max
Unit
V
DD
Any V
DD
supply voltage, related to substrate
-0.5
5
Vhh
V
in
Voltage at any input pin
-0.5
VDD + 0.5
V
T
stg
Storage Temperature
-40
125
C
T
L
Lead Temperature (10 second soldering)
300
C
ILU
Latch-up current @ 80C
100
mA
Symbol
Parameter Description
Min
Max
Unit
AV
DD
AVDD supply voltage, related to substrate
3.0
3.6
V
DV
DD
DVDD supply voltage, related to substrate
2.7
3.6
V
V
in
, V
out
Voltage at any input and output pin
0
V
DD
V
P
d
Power Dissipation
0.4
0.6
W
T
amb
Ambient Temperature
-40
85
C
T
j
Junction temperature
-40
110
C
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
IL
Low level input voltage
0.2*DV
DD
V
V
IH
High level input voltage
0.8*DV
DD
V
V
H
Hysteresis
1.0
1.3
V
C
inp
Input capacitance
3
pF
Symbol
Parameters
Test Cond
Min
Max
Unit
V
OL
Low level output voltage
Iout = 4 mA
.15*DV
DD
V
V
OH
High level output voltage
Iout = 4 mA
.85*DV
DD
V
C
load
Load capacitance
1.0
30
pF
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