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MTC50150
September 2004
1
GENERAL FEATURES
1.1 WAN modem feature set
Embedded transceiver ANSI T1.413, ITU G.dmt
Annex A/B incl. Deutsche Telecom UR-2
compliant, splitterless ITU G.Lite
ADSL analog front end compatibility:
MTC20174, ADSL front end, 7
th
generation,
integrated line driver, DCXO
1.2 WAN connectivity
Point to point protocol over Ethernet
Point to point protocol over ATM
Relay via PPP session control on terminal
CIP classical IP over Ethernet
Full ICSA firewall
1.3 Session Control
PPPoE point to point protocol over Ethernet
PPPoA point to point protocol over ATM
PPPoA relay via PPP session control on
terminal.
1.4 ATM features
Adaptation Layers: AAL5 (data), supported in
hardware
Encapsulation: RFC1483 and RFC2684, multi
protocol encapsulation over ATM (MPOA) over
AAL5 bridged and routed modes
ATM circuit: 8 PVC
Available services (Qos): UBR
1.5 LAN feature set
1 Ethernet 10/100 MII (HPNA compatible)
2 UARTs, Bluetooth compatible
Bridging: Transparent bridge: IEEE 801.1d,
spanning tree, learning/filter bridge in hardware
Embedded router: RIP1, RIP2, static routing
NAT/PAT with extended ALG support
DHCP server/client
IP protocol: TCP/IP, ARP sharing access,
ICMP, IGMP
Support up to 128 MAC stations.
Embedded http server for configuration
1.6 Configuration and Provisioning
Configuration: remote configuration via JavaTM
enabled browser
Firmware update: remote upload via network.
Management: SNMP, UNI3.1, ILMI 4.0
(management and auto configuration)
1.7 Customization
Customization with comprehensive API set
Development tool based on Windows
environment on PC
Exposed BSP layer
Flexible development licenses based on kernel
software in object or source format.
2
APPLICATION
Low cost ADSL residential gateway
Residential gateway with broadband ADSL
WAN transceiver
Wan to LAN bridge and router with ADSL WAN
transceiver and Ethernet MAC
Wireless LAN access point with ADSL WAN
transceiver and Ethernet MAC
DATA BRIEF
ADSL GATEWAY PROCESSOR
Figure 1. Package
Table 1. Order Codes
Part Number
Package
MTC50150-TB-C2
PBGA208
PBGA208 (17x17x1.97mm)
Rev. 1
MTC50150
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Figure 2. Block diagram
3
DESCRIPTION
The MTC50150 is a low cost ADSL bridge and LAN router. One 10/100Mbits Ethernet port allows the con-
nection of a LAN to the WAN in bridged or routed mode. The data traffic can be routed through a local
terminal by using the LAN port. The presence of NAT and DHCP and the API slots for firewall functions
allow for a high-speed connection of LAN connected devices, like PC, to the public Internet in an isolated
and secure environment.
The chip is built around an ARM946ES RISC processor. It embeds a complete ADSL transceiver and LAN
interfaces with an MII allowing multiple medium utilization. A comprehensive software package is available
with the SOC solution, which has been developed with customization in mind. Several software license
plans are available as well as a user friendly development environment.
4
HARDWARE DESCRIPTION
The MTC50150 processor combines a DynaMiTeTM ADSL transceiver with a dedicated ARM946ES RISC
processor. To maintain high data throughput, the RISC processor includes 16Kbyte cache memory for
programming and 16Kbyte memory for data. Processing of most of the layer 2 protocols on the ATM (SAR
and AAL) and IP (Mac filter and bridge) sides are performed by specific hardware blocks, relieving the pro-
cessors from these tasks. The chip provides minimal external components and maximum flexibility. In ad-
dition, it contains one Ethernet 10/100 Base-T MAC and the exposed MII interface allows the connection
to alternate LAN mediums like HPNA, WLAN, and HPLUG. The MTC-50150 device is targeted for low-
cost residential gateways. Its primary design goal is to minimize cost. Secondary design goals are:
Low system cost using a reduced BOM and optimized SOC technology
Low power to facilitate primary service capabilities and thermal system issues
Low EMI to simplify packaging and qualification of systems
PLL
APB BRIDGE
ISA
(FLASH)
COMMUNICATION
CONTROLLER
ARM946ES
DMA
SDRAM INTERFACE
ROM
JTAG
UART
GPIO
10/100
BRIDGE &
MAC
ADSL
DMT-U
AAL5
SAR
D02TL543
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MTC50150
5
HARDWARE FEATURES
ARM946ES RISC processor dedicated to network processing, API and DSL modem control
Hardware ATM processor: SAR function with AAL5 processing
Hardware packet processor: Ethernet MAC, learning and filter bridge
One 10/100 Base-T Ethernet MACs with MII interface for external PHY or multi-port switch
One 8 or 16-bit wide Flash port, ISA compatible for up to 16Mbyte addressable memory
One 32-bit wide SDRAM interface with 32Mbyte addressable memory
Interface to MTC20174 DynaMiTeTM ADSL analog front end (AFE) chip
Multi-channel DMA engine integrated with peripherals
Low power: 1.8V +/-10% core voltage, 3.3V +/- 10% I/O voltage
128 instructions (32 bits) of boot ROM
GPIO with support LED
Cc-based Multi ICE/compiler support with assembler and debugger
Software chip and system simulators for software development and debug
JTAG board-level test interface
140MHz system clock (processor cycle clock)
Sleep mode with wake on LAN wake on WAN feature
Programmable system frequency clock: 140, 105, 70, 35 and 129MHz (fall back mode).
6
SOFTWARE ARCHITECTURE
The software is organized in 5 clusters:
User interface API
System services
Network services
TCP/IP socket
ATM encapsulation
A description of the cluster contents is given in the software features section.
MTC50150
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Figure 3. Embedded software block diagram
7
SOFTWARE FEATURES
7.1 User Interface API
A development kit dedicated to the platform allows access through the API to specific code sections to
allow software customization. The development kit provides source code for a packet phone application,
drivers and diagnostic software. Other stacks are delivered in the object code. A specific development en-
vironment is provided. It includes project profiling, managing, C compiler/assembler and tools as well a
source level debugger.
7.2 System Services
MAPI offers an easy interface to control the operations necessary to setup the ADSL link and monitor the
operation conditions. The software provides an optimized control sequence to insure optimum operation
of the DynaMiTeTM chip set.
MIB2: RFC 1213: Management Information Bases (MIB2) is implemented in the device.
RTOS: Implemented RTOS is Posix compliant. The user can access various parts of the software blocks
through specific APIs. Alternate RTOS are planned.
Flash Initialization. Software is stored on an external Flash. At boot-up, the stored software is downloaded
to the device. By using compilation options, software can be executed from the internal RAM (intensive
operations) or executed from the flash. Execution is optimized by the use of an intermediate cache mem-
ory.
Startup initialization: Optional software images can be selected at startup of the device.
Broad Support Program: A BSP layer is provided to allow easy porting of proprietary software on the SOC
architecture. The BSP provides a unique hardware abstraction layer model valid for the entire product line.
This approach allows reuse of the custom solfware through the entire MTC-50xxx product line(*).
(*) starting with MTC-50150
USER INTERFACE
SYSTEM
SERVICES
RTOS
MIB
CTRL-E
DOWNLOAD
FLASH MGR
ILMI
UNI3.1
DIAGNOSTIC
NETWORK
SERVICES
HTTP SRV
SNMP
TFTP
DNS
ROUTER
RIP1.2
TCP
UDP
UDP
FIREWALL
NAT
DHCP
IP SOCKET
PPPoE
PPPoA
PPTP
RAS
ATM ENCAPSULATION
BRIDGING, SPANNING
LEARNING TREE
AAL5/SAR
MAC
UTOPIA MASTER DRIVER
MII DRIVER
BRIDGE FIRMWARE
ROUTER ADD-ON
D02TL535
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MTC50150
7.3 Network Services
7.3.1 ILMI
Embedded software provides an ILMI 4.0 implementation which handles address registration (switch to
end device) and notification (end device to switch) as well as auto-configuration. ILMI uses SNMP over
AAL-5 for transport.
7.3.2 UNI Signaling
Stackware includes support for standard ATM UNI signaling standards, including UNI 3.1.
7.3.3 RIP1/RIP2 IP Router
IP router software provides implementations of RIP1 and RIP2. The IP router is an IPv4 router. Support
for new station discovery is provided.
7.4 TCP/IP Socket
7.4.1 TCP
Transport Control Protocol (TCP) is accessed using a standard socket interface to allow easy integration
of existing Layer 3 and higher software into the basic protocol stack.
7.4.2 IP
Internal protocol: IP and IP routing are both part of the network layer (layer 3). IP is actually responsible
for delivering packets for which the router defines the direction.
7.4.3 DHCP RFC 2131, 2132
Dynamic Host Control Protocol (DHCP) provides both client & server functions. The client is typically used
to obtain an IP address from an ISP. The DHCP server is used to assign local IP client devices with des-
ignated IP addresses. The server lends addresses for a limited time. NAT registers local terminal IP ad-
dresses and maintains a translation table to allow sending and receiving data on the public network by
sharing only the residential gateway assigned public IP address.
7.4.4 NAT: RFC1631, 2663
The Network Address Translator (NAT) implements Network and Port Address Translation (NAT/PAT).
NAT allows a single public IP address on the WAN side to be shared among many devices on the LAN
side. Combined with a DHCP server local devices are assigned a private address, hidden to the public
internet and changed frequently. The combination of DHCP and NAT provides a powerful isolation barrier
to external assault. NAT PAT features a number of AGL.
7.5 ATM Encapsulation and spanning-tree
RFC 1483/2684 provides a simple robust method of connecting end stations over an ATM network. User
data in the form of Ethernet packets are encapsulated into AAL-5 PDUs for transport over ATM. RFC
1483/2684 provides no AAA function (authentication, authorization & accounting).
7.5.1 Spanning-tree bridge (802.1d)
Bridge module provides a transparent bridge between two physically disjoint networks with spanning-tree
option. The spanning-tree algorithm handles redundancy and also increases robustness. It provides high
performance as well as flexibility to group interfaces for example to bridge the WAN only to LAN interfaces
but not to other WAN interfaces.
The ATM driver passes data between application software tasks on the processor and a physical AAL5
hardware block.
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