Document Outline

• FEATURES SUMMARY
  • Figure 1. Packages
• SUMMARY DESCRIPTION
  • Table 1. Product Range
  • Figure 2. PQFP52 Connections
  • Figure 3. PLCC52 Connections
  • Figure 4. TQFP64 Connections
• PIN DESCRIPTION
  • Table 2. Pin Description (for the PLCC52 package - Note 1)
  • Figure 5. PSD Block Diagram
• PSD ARCHITECTURAL OVERVIEW
  • Memory
  • Page Register
  • PLDs
  • I/O Ports
  • MCU Bus Interface
    • Table 3. PLD I/O
  • JTAG Port
  • In-System Programming (ISP)
  • Power Management Unit (PMU)
    • Table 4. JTAG SIgnals on Port C
    • Table 5. Methods of Programming Different Functional Blocks of the PSD
• DEVELOPMENT SYSTEM
  • Figure 6. PSDsoft Express Development Tool
• PSD Register Description and Address Offset
  • Table 6. I/O Port Latched Address Output Assignments (Note1)
  • Table 7. Register Address Offset
• DETAILED OPERATION
  • Memory Blocks
    • Table 8. Memory Block Size and Organization
  • Primary Flash Memory and Secondary Flash memory Description
  • Memory Block Select Signals
    • Ready/Busy (PC3)
    • Memory Operation
    • Table 9. Instructions
• INSTRUCTIONS
  • Power-up Mode
  • READ
  • Read Memory Contents
  • Read Primary Flash Identifier
  • Read Memory Sector Protection Status
  • Reading the Erase/Program Status Bits
    • Table 10. Status Bit
  • Data Polling Flag (DQ7)
  • Toggle Flag (DQ6)
  • Error Flag (DQ5)
  • Erase Time-out Flag (DQ3)
• PROGRAMMING FLASH MEMORY
  • Data Polling
    • Figure 7. Data Polling Flowchart
  • Data Toggle
  • Unlock Bypass (PSD833F2x, PSD834F2x, PSD853F2x, PSD854F2x)
    • Figure 8. Data Toggle Flowchart
• ERASING FLASH MEMORY
  • Flash Bulk Erase
  • Flash Sector Erase
  • Suspend Sector Erase
  • Resume Sector Erase
• SPECIFIC FEATURES
  • Flash Memory Sector Protect
  • Reset Flash
  • Reset (RESET) Signal (on the PSD83xF2 and PSD85xF2)
    • Table 11. Sector Protection/Security Bit Definition � Flash Protection Register
    • Table 12. Sector Protection/Security Bit Definition � PSD/EE Protection Register
• SRAM
• SECTOR SELECT AND SRAM SELECT
  • Example
  • Memory Select Configuration for MCUs with Separate Program and Data Spaces
    • Figure 9. Priority Level of Memory and I/O Components
  • Configuration Modes for MCUs with Separate Program and Data Spaces
    • Separate Space Modes
    • Combined Space Modes
    • Figure 10. 8031 Memory Modules � Separate Space
    • Figure 11. 8031 Memory Modules � Combined Space
    • Table 13. VM Register
• PAGE REGISTER
  • Figure 12. Page Register
• PLDS
  • The Turbo Bit in PSD
    • Table 14. DPLD and CPLD Inputs
    • Figure 13. PLD Diagram
  • Decode PLD (DPLD)
    • Figure 14. DPLD Logic Array
  • Complex PLD (CPLD)
    • Figure 15. Macrocell and I/O Port
  • Output Macrocell (OMC)
    • Table 15. Output Macrocell Port and Data Bit Assignments
  • Product Term Allocator
  • Loading and Reading the Output Macrocells (OMC)
  • The OMC Mask Register
  • The Output Enable of the OMC
    • Figure 16. CPLD Output Macrocell
  • Input Macrocells (IMC)
    • Figure 17. Input Macrocell
    • Figure 18. Handshaking Communication Using Input Macrocells
• MCU BUS INTERFACE
  • Table 16. MCUs and their Control Signals
  • PSD Interface to a Multiplexed 8-Bit Bus
    • Figure 19. An Example of a Typical 8-bit Multiplexed Bus Interface
  • PSD Interface to a Non-Multiplexed 8-Bit Bus
  • Data Byte Enable Reference
  • MCU Bus Interface Examples
    • Table 17. Eight-Bit Data Bus
    • Figure 20. An Example of a Typical 8-bit Non-Multiplexed Bus Interface
  • 80C31
    • Figure 21. Interfacing the PSD with an 80C31
  • 80C251
    • Figure 22. Interfacing the PSD with the 80C251, with One READ Input
    • Figure 23. Interfacing the PSD with the 80C251, with RD and PSEN Inputs
    • Table 18. 80C251 Configurations
  • 80C51XA
    • Figure 24. Interfacing the PSD with the 80C51X, 8-bit Data Bus
  • 68HC11
    • Figure 25. Interfacing the PSD with a 68HC11
• I/O PORTS
  • General Port Architecture
  • Port Operating Modes
    • Figure 26. General I/O Port Architecture
  • MCU I/O Mode
  • PLD I/O Mode
  • Address Out Mode
    • Table 19. Port Operating Modes
    • Table 20. Port Operating Mode Settings
    • Table 21. I/O Port Latched Address Output Assignments
  • Address In Mode
  • Data Port Mode
  • Peripheral I/O Mode
    • Figure 27. Peripheral I/O Mode
  • JTAG In-System Programming (ISP)
  • Port Configuration Registers (PCR)
  • Control Register
  • Direction Register
  • Drive Select Register
    • Table 22. Port Configuration Registers (PCR)
    • Table 23. Port Pin Direction Control, Output Enable P.T. Not Defined
    • Table 24. Port Pin Direction Control, Output Enable P.T. Defined
    • Table 25. Port Direction Assignment Example
    • Table 26. Drive Register Pin Assignment
  • Port Data Registers
  • Data In
  • Data Out Register
    • Output Macrocells (OMC)
  • OMC Mask Register
    • Table 27. Port Data Registers
  • Input Macrocells (IMC)
  • Enable Out
  • Ports A and B � Functionality and Structure
    • Figure 28. Port A and Port B Structure
  • Port C � Functionality and Structure
    • Figure 29. Port C Structure
  • Port D � Functionality and Structure
    • Figure 30. Port D Structure
  • External Chip Select
    • Figure 31. Port D External Chip Select Signals
• POWER MANAGEMENT
  • Automatic Power-down (APD) Unit and Power-down Mode
    • Power-down Mode
    • Table 28. Power-down Mode�s Effect on Ports
    • Figure 32. APD Unit
    • Table 29. PSD Timing and Stand-by Current during Power-down Mode
  • For Users of the HC11 (or compatible)
  • Other Power Saving Options
    • Figure 33. Enable Power-down Flow Chart
  • PLD Power Management
    • SRAM Standby Mode (Battery Backup)
    • Table 30. Power Management Mode Registers PMMR0 (Note 1)
    • Table 31. Power Management Mode Registers PMMR2 (Note 1)
  • PSD Chip Select Input (CSI, PD2)
  • Input Clock
  • Input Control Signals
    • Table 32. APD Counter Operation
• RESET TIMING AND DEVICE STATUS AT RESET
  • Power-Up Reset
  • Warm Reset
  • I/O Pin, Register and PLD Status at Reset
  • Reset of Flash Memory Erase and Program Cycles (on the PSD834Fx)
    • Figure 34. Reset (RESET) Timing
    • Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode
• PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
  • Standard JTAG Signals
  • JTAG Extensions
  • Security and Flash memory Protection
    • Table 34. JTAG Port Signals
• INITIAL DELIVERY STATE
  • Table 35. JTAG Enable Register
• AC/DC PARAMETERS
  • Figure 35. PLD ICC /Frequency Consumption (5V range)
  • Figure 36. PLD ICC /Frequency Consumption (3V range)
  • Table 36. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode On)
  • Table 37. Example of PSD Typical Power Calculation at VCC = 5.0V (Turbo Mode Off)
• MAXIMUM RATING
  • Table 38. Absolute Maximum Ratings
• DC AND AC PARAMETERS
  • Table 39. Operating Conditions (5V devices)
  • Table 40. Operating Conditions (3V devices)
  • Table 41. AC Signal Letters for PLD Timing
  • Table 42. AC Signal Behavior Symbols for PLD Timing
  • Table 43. AC Measurement Conditions
  • Table 44. Capacitance
  • Figure 37. AC Measurement I/O Waveform
  • Figure 38. AC Measurement Load Circuit
  • Figure 39. Switching Waveforms � Key
  • Table 45. DC Characteristics (5V devices)
  • Table 46. DC Characteristics (3V devices)
  • Figure 40. Input to Output Disable / Enable
  • Table 47. CPLD Combinatorial Timing (5V devices)
  • Table 48. CPLD Combinatorial Timing (3V devices)
  • Figure 41. Synchronous Clock Mode Timing � PLD
  • Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices)
  • Table 50. CPLD Macrocell Synchronous Clock Mode Timing (3V devices)
  • Figure 42. Asynchronous Reset / Preset
  • Figure 43. Asynchronous Clock Mode Timing (product term clock)
  • Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices)
  • Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices)
  • Figure 44. Input Macrocell Timing (product term clock)
  • Table 53. Input Macrocell Timing (5V devices)
  • Table 54. Input Macrocell Timing (3V devices)
  • Figure 45. READ Timing
  • Table 55. READ Timing (5V devices)
  • Table 56. READ Timing (3V devices)
  • Figure 46. WRITE Timing
  • Table 57. WRITE Timing (5V devices)
  • Table 58. WRITE Timing (3V devices)
  • Table 59. Program, WRITE and Erase Times (5V devices)
  • Table 60. Program, WRITE and Erase Times (3V devices)
  • Figure 47. Peripheral I/O READ Timing
  • Table 61. Port A Peripheral Data Mode READ Timing (5V devices)
  • Table 62. Port A Peripheral Data Mode READ Timing (3V devices)
  • Figure 48. Peripheral I/O WRITE Timing
  • Table 63. Port A Peripheral Data Mode WRITE Timing (5V devices)
  • Table 64. Port A Peripheral Data Mode WRITE Timing (3V devices)
  • Figure 49. Reset (RESET) Timing
  • Table 65. Reset (RESET) Timing (5V devices)
  • Table 66. Reset (RESET) Timing (3V devices)
  • Table 67. VSTBYON Timing (5V devices)
  • Table 68. VSTBYON Timing (3V devices)
  • Figure 50. ISC Timing
  • Table 69. ISC Timing (5V devices)
  • Table 70. ISC Timing (3V devices)
  • Table 71. Power-down Timing (5V devices)
  • Table 72. Power-down Timing (3V devices)
• PACKAGE MECHANICAL
  • Figure 51. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Drawing
  • Table 73. PQFP52 - 52-pin Plastic, Quad, Flat Package Mechanical Dimensions
  • Figure 52. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Drawing
  • Table 74. PLCC52 - 52-lead Plastic Lead, Chip Carrier Package Mechanical Dimensions
  • Figure 53. TQFP64 - 64-lead Thin Quad Flatpack, Package Outline
  • Table 75. TQFP64 - 64-lead Thin Quad Flatpack, Package Mechanical Data
• PART NUMBERING
  • Table 76. Ordering Information Scheme
• APPENDIX A. PQFP52 PIN ASSIGNMENTS
  • Table 77. PQFP52 Connections (Figure 2)
• APPENDIX B. PLCC52 PIN ASSIGNMENTS
  • Table 78. PLCC52 Connections (Figure 3)
• APPENDIX C. TQFP64 PIN ASSIGNMENTS
  • Table 79. TQFP64 Connections (Figure 4)
• REVISION HISTORY
  • Table 80. Document Revision History