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SMP100LC
TRISILTM FOR TELECOM EQUIPMENT PROTECTION
REV. 11
SMB
(JEDEC DO-214AA)
June 2005
FEATURES
Bidirectional crowbar protection
Voltage range from 8V to 400V
Low capacitance from 20pF to 45pF @ 50V
Low leakage current : I
R
= 2A max
Holding current: I
H
= 150 mA min
Repetitive peak pulse current:
I
PP
= 100 A (10/1000s)
MAIN APPLICATIONS
Any sensitive equipment requiring protection
against lightning strikes and power crossing.
These devices are dedicated to central office pro-
tection as they comply with the most stressfull
standards.
Their Low Capacitances make them suitable for
ADSL.
DESCRIPTION
The SMP100LC is a series of low capacitance
transient surge arrestors designed for the protec-
tion of high debit rate communication equipment.
Its low capacitance avoids any distortion of the sig-
nal and is compatible with digital transmission line
cards (xDSL, ISDN...).
SMP100LC series tested and confirmed compati-
ble with Cooper Bussmann Telecom Circuit Pro-
tector TCP 1.25A.
BENEFITS
Trisils are not subject to ageing and provide a fail
safe mode in short circuit for a better protection.
They are used to help equipment to meet main
standards such as UL60950, IEC950 / CSA C22.2
and UL1459. They have UL94 V0 approved resin.
SMB package is JEDEC registered (DO-214AA).
Trisils comply with the following standards GR-
1089 Core, ITU-T-K20/K21, VDE0433, VDE0878,
IEC61000-4-5 and FCC part 68.
Table 1: Order Codes
Part Number
Marking
SMP100LC-8
PL8
SMP100LC-25
L25
SMP100LC-35
L35
SMP100LC-65
L06
SMP100LC-90
L09
SMP100LC-120
L12
SMP100LC-140
L14
SMP100LC-160
L16
SMP100LC-200
L20
SMP100LC-230
L23
SMP100LC-270
L27
SMP100LC-320
L32
SMP100LC-360
L36
SMP100LC-400
L40
Figure 1: Schematic Diagram
SMP100LC
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Table 2: In compliance with the following standards
Table 3: Absolute Ratings (T
amb
= 25C)
STANDARD
Peak Surge
Voltage
(V)
Waveform
Voltage
Required
peak current
(A)
Current
waveform
Minimum serial
resistor to meet
standard (
)
GR-1089 Core
First level
2500
1000
2/10 s
10/1000 s
500
100
2/10 s
10/1000 s
0
0
GR-1089 Core
Second level
5000
2/10 s
500
2/10 s
0
GR-1089 Core
Intra-building
1500
2/10 s
100
2/10 s
0
ITU-T-K20/K21
6000
1500
10/700 s
150
37.5
5/310 s
0
0
ITU-T-K20
(IEC61000-4-2)
8000
15000
1/60 ns
ESD contact discharge
ESD air discharge
0
0
VDE0433
4000
2000
10/700 s
100
50
5/310 s
0
0
VDE0878
4000
2000
1.2/50 s
100
50
1/20 s
0
0
IEC61000-4-5
4000
4000
10/700 s
1.2/50 s
100
100
5/310 s
8/20 s
0
0
FCC Part 68, lightning
surge type A
1500
800
10/160 s
10/560 s
200
100
10/160 s
10/560 s
0
0
FCC Part 68, lightning
surge type B
1000
9/720 s
25
5/320 s
0
Symbol
Parameter
Value
Unit
I
PP
Repetitive peak pulse current (see figure 2)
10/1000 s
8/20 s
10/560 s
5/310 s
10/160 s
1/20 s
2/10 s
100
400
140
150
200
400
500
A
I
FS
Fail-safe mode : maximum current (note 1)
8/20 s
5
kA
I
TSM
Non repetitive surge peak on-state current (sinusoidal)
t = 0.2 s
t = 1 s
t = 2 s
t = 15 mn
24
15
12
4
A
I
2
t
I
2
t value for fusing
t = 16.6 ms
t = 20 ms
20
21
A
2
s
T
stg
T
j
Storage temperature range
Maximum junction temperature
-55 to 150
150
C
T
L
Maximum lead temperature for soldering during 10 s.
260
C
Note 1: in fail safe mode, the device acts as a short circuit
SMP100LC
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Table 4: Thermal Resistances
Table 5: Electrical Characteristics (T
amb
= 25C)
Symbol
Parameter
Value
Unit
R
th(j-a)
Junction to ambient (with recommended footprint)
100
C/W
R
th(j-l)
Junction to leads
20
C/W
Symbol
Parameter
V
RM
Stand-off voltage
V
BR
Breakdown voltage
V
BO
Breakover voltage
I
RM
Leakage current
I
PP
Peak pulse current
I
BO
Breakover current
I
H
Holding current
V
R
Continuous reverse voltage
I
R
Leakage current at V
R
C
Capacitance
Types
I
RM
@ V
RM
I
R
@ V
R
Dynamic
V
BO
Static
V
BO
@ I
BO
I
H
C
C
max.
max.
max.
max.
max.
min.
typ.
typ.
note1
note 2
note 3
note 4
note 5
note 6
A
V
A
V
V
V
mA
mA
pF
pF
SMP100LC-8
2
6
5
8
25
15
800
50 (typ.)
NA
75
SMP100LC-25
22
25
40
35
150
NA
65
SMP100LC-35
32
35
55
55
NA
55
SMP100LC-65
55
65
85
85
45
90
SMP100LC-90
81
90
120
125
40
80
SMP100LC-120
108
120
155
160
35
75
SMP100LC-140
120
140
185
190
30
65
SMP100LC-160
144
160
205
200
30
65
SMP100LC-200
180
200
255
250
30
60
SMP100LC-230
207
230
295
285
30
60
SMP100LC-270
243
270
345
335
30
60
SMP100LC-320
290
320
400
390
25
50
SMP100LC-360
325
360
460
450
25
50
SMP100LC-400
360
400
540
530
20
45
Note 1: IR measured at VR guarantee VBR min
VR
Note 2: see functional test circuit 1
Note 3: see test circuit 2
Note 4: see functional holding current test circuit 3
Note 5: VR = 50V bias, VRMS=1V, F=1MHz
Note 6: VR = 2V bias, VRMS=1V, F=1MHz
SMP100LC
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Figure 2: Pulse waveform
Figure 3: Non repetitive surge peak on-state
current versus overload duration
Figure 4: On-state voltage versus on-state
current (typical values)
Figure 5: Relative variation of holding current
versus junction temperature
Figure 6: Relative variation of breakover
voltage versus junction temperature
Figure 7: Relative variation of leakage current
versus junction temperature (typical values)
100
50
%I
PP
t
r
t
p
0
t
Repetitive peak pulse current
tr = rise time (s)
tp = pulse duration time (s)
I
(A)
TSM
1E-2
1E-1
1E+0
1E+1
1E+2
1E+3
0
10
20
30
40
50
60
70
F=50Hz
T initial = 25C
j
t(s)
10
100
0
1
2
3
4
5
6
7
8
V (V)
T
I (A)
T
T initial = 25C
j
I [T ] / I [T =25C]
H
H
j
j
-25
0
25
50
75
100
125
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
T (C)
j
-25
0
25
50
75
100
125
0.96
0.98
1.00
1.02
1.04
1.06
1.08
V
[ ] / V
[ =25C]
BO
BO
T
T
j
j
T (C)
j
I [ ] / I [ =25C]
R
R
T
T
j
j
25
50
75
100
125
1
10
100
1000
2000
T (C)
j
SMP100LC
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APPLICATION NOTE
In such a stage, parallel function is assumed by one or several Trisil, and is used to protect against short
duration surge (lightning). During this kind of surges the Trisil limits the voltage across the device to be
protected at its break over value and then fires. The fuse assumes the series function, and is used to pro-
tect the module against long duration or very high current mains disturbances (50/60Hz). It acts by safe
circuits opening. Lightning surge and mains disturbance surges are defined by standards like GR1089,
FCC part 68, ITU-T K20.
Figure 8: Variation of thermal impedance
junction to ambient versus pulse duration
(Printed circuit board FR4, SCu=35m,
recommended pad layout)
Figure 9: Relative variation of junction
capacitance versus reverse voltage applied
(typical values)
In wireline applications, analog or digital, both central office and subscriber sides have to be protected.
This function is assumed by a combined series / parallel protection stage.
1E-3
1E-2
1E-1
1E+0
1E+1
1E+2
5E+2
1
10
100
t (s)
p
Z
/R
th(j-a)
th(j-a)
C [V ] / C [V =2V]
R
R
1
2
5
10
20
50
100
300
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V (V)
R
F =1MHz
V
= 1V
T = 25C
j
RMS
Line
Protection stage
Protection stage
Ring
relay
Line
Ex. Analog line card
Ex. ADSL line card or terminal
Fuse TCP 1.25A
T1
T2
SMP100LC-xxx
Typical circuit for subscriber side
Fuse TCP 1.25A
Tip S
Gnd
SMP100LC-xxx
Ring S
SMP100LC-xxx
Fuse TCP 1.25A
Tip L
Gnd
Ring L
Typical circuit for central office side
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