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ST1284-xxA8/T8
July 2002 - Ed: 1B
s
One device for parallel port termination
s
Compliant with IEEE1284 standard
s
EMI / RFI noise filtering
s
Highly integrated solution in 28 pin QSOP and
TSSOP packages
s
One single device provides the proper termina-
tion for 8 datalines, 1 strobe line, 4 control lines
and 4 statuts lines
s
In system ESD protection of 15 kV (air dis-
charge) as per IEC61000-4-2 level 4
FEATURES
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
Gnd
Vcc
Vcc
Vcc
Vcc
Vcc
R1
C
R1
C
R1
R2
C
R1
R1
R1
R1
R1
R2
R1
R2
R1
R2
R1
R1
R2
C
Rs
C
Rs
C
Rs
C
Rs
C
Rs
C
Rs
C
Rs
C
Rs
Rs
C
C
C
C
C
C
SCHEMATIC DIAGRAM
PARALLEL PORT SINGLE TERMINATION
NETWORK WITH 15kV ESD PROTECTION
A.S.D.
TM
ECP/EPP Parallel Port termination on:
s
Desktops
s
Notebooks
s
Workstations
s
Servers
s
PC Peripherals
s
Set Top Box
MAIN APPLICATIONS
The ST1284-xxA8/T8 is a highly integrated termi-
nation for enhanced high speed parallel ports. The
integrated termination complies to the IEEE1284
Standard
recommendations
and
government
EMC compatibility requirements. It is built around
two basic cells. The first one (Cell 1) provides line
termination, EMI filtering and ESD protection for
the Strobe and Datalines while the second one
(Cell 2) provides EMI filtering and ESD protection
for the Control and Status lines. In addition,
ST1284-xxA8 provides extra protection against
ESD. When tested according to IEC61000-4-2,
they withstand 8kV contact discharges and
15kV air-discharges, thereby providing to the
system the necessary robustness to meet up to
level 4 of IEC61000-4-2, without the need for addi-
tional ESD protection components. Cells 1 and 2
are described in more detail in figures 1 and 2.
DESCRIPTION
QSOP28 / TSSOP28
R1
R2
Rs
C
Code 01
4.7k
4.7k
33
180pF
Code 02
2.2k
2.2k
33
220pF
Code 03
1k
5.1k
39
150pF
Tolerance
10%
10%
10%
20%
- IEC61000-4-2
15kV (air discharge)
8kV
(contact discharge)
- MIL STD 883E - Method 3015-7 : Class 3
(human body model).
COMPLIES
WITH
THE
FOLLOWING
ESD
STANDARDS :
ST1284-xxA8/T8
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Symbol
Parameter
Value
Unit
V
PP
ESD discharge IEC61000-4-2, air discharge
16
kV
ESD discharge IEC61000-4-2, contact discharge
9
kV
ESD discharge - MIL STD 883E - Method 3015-7
25
kV
V
cc
Supply voltage
5.5
V
P
r
Power rating per resistor
100
mW
P
P
Package Power rating
1
W
T
op
Operating temperature range
0 to +70
C
T
stg
Storage temperature range
-55 to +150
C
T
j
Maximum operating junction temperature
125
C
ABSOLUTE MAXIMUM RATINGS (T
amb
25C)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
I
R
Leakage current
V
cc
= 5.0V
10
A
V
BR
Breakdown voltage
I
R
= 1mA
6
V
V
F
Forward voltage drop
I
F
= 50mA
0.9
V
ELECTRICAL CHARACTERISTICS (T
amb
= 25C)
The ST1284-xxA8/T8 is built around the two basic cells described below which integrate the recom-
mended IEEE1284 network and the ESD protection compatible with IEC61000-4-2 level 4
BASIC CELL CONFIGURATIONS
C
IEEE1284
Recommendation
Vcc
Gnd
Rp
Rs
Fig. 1:Cell 1 for line termination, EMI filtering and
ESD protection for the Datalines and Strobe sig-
nals. There are 9 of these cells inside the
ST1284-xxA8/T8
C
IEEE1284
Recommendation
Vcc
Gnd
Rp
Fig. 2: Cell 2 for EMI filtering and ESD protection
of the Control and Status signals. There are 8 of
these cells inside the ST1284-xxA8/T8
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ST1284-xxA8/T8
14 Autofeed
15 Error
16 Reset
17 Select in
1 Strobe
2 Bit 1
3 Bit 2
4 Bit 3
5 Bit 4
6 Bit 5
7 Bit 6
8 Bit 7
9 Bit 8
13 Select paper
14
1
13
25
1
28
2
27
20
26
25
24
23
21
19
18
17
16
3
4
5
6
7
9
11
13
14
8
10
12
15
22
10 Acknowledge
11 Busy
12 Paper Out
Vcc
Vcc
Vcc
Gnd
ST1284-xxA8/T8
FUNCTIONAL DIAGRAM
The functional diagram here above presents a IEEE1284-A connector pinout and show how to connect
the ST1284-xxA8/T8 in order to correctly terminate and filter the 17 signal lines. The IEEE1284-A con-
nector is the PC standard for the host connection.
Control and status lines (from 10 to 17) only require a pull-up resistor (Rp) and a filter capacitor (C).
The data lines (from 2 to 9) and the STROBE (pin 1) also require a termination series resistor (Rs)
in addition to the pull-up resistor and a filter capacitor. The Vcc is connected to pin 20 and the
ground to pin 22.
The ST1284-xxA8/T8 can be used with all 3 types of connectors defined in the IEEE1284 standard:
- IEEE1284-A is a 25DB connector which is the PC standard for the host connection.
- IEEE1284-B is a 36 pin, 0.085 inch centerline connector used on the peripheral device.
- IEEE1284-C is a new 36 pin, 0.050 inch centerline connector which can be used for both host and peripher-
als.
APPLICATION INFORMATION
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ST1284-xxA8/T8
FREQUENCY BEHAVIOR OF DATA AND STROBE SIGNALS
TECHNICAL INFORMATION
ST1284
SPECTRUM
ANALYSER
TRACKING
GENERATOR
Vg
Vout
Vin
50
50
+5V
Fig. A1: Measurement conditions
1
3
10
30
100
300
1,000
- 30.00
- 25.00
- 20.00
- 15.00
- 10.00
- 5.00
0.00
dB
F (MHz)
1284 - 01
1284 - 02
1284 - 03
Fig. A2: Typical frequency response curve for data
and strobe signals.
In addition to the requirements of termination and EMC compatibility, computing devices are required to be
tested for ESD susceptibility. This test is described in the IEC61000-4-2 and is already in place in Europe.
This test requires that a device tolerates ESD events and remain operational without user intervention.
The ST1284-xxA8/T8 is particularly optimized to perform ESD protection. ESD protection is based on the
use of device which clamps at :
Vouput
V
R I
BR
d
PP
=
+
.
This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the
first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R.
Such a configuration makes the voltage very low at the output.
ESD PROTECTION
ESD Surge
Vinput
Voutput
Rload
Rg
R
S1
Rd
V
BR
V
BR
V
PP
Device
to be
protected
ST1284-xxA8/T8
Rd
S2
Fig. A3: ST1284 ESD clamping behavior
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ST1284-xxA8/T8
To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical
dynamical resistance value Rd. By taking into account these following hypothesis : Rt>Rd, Rg>Rd and
Rload>Rd, it gives these formulas:
Vinput
R V
R V
R
g
BR
d
PP
g
=
+
.
.
Voutput
R V
R Vinput
R
t
BR
d
t
=
+
.
.
The results of the calculation done for V
PP
=8kV, Rg=330
(IEC61000-4-2 standard), V
BR
=7V (typ.)
and Rd = 1
(typ.) give:
Vinput = 31.2 V
Voutput = 7.95 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be few
tenths of volts during few ns at the input side. This parasitic effect is not present at the output side due the
low current involved after the resistance R.
The measurements done here after show very clearly (Fig. A5) the high efficiency of the ESD protection :
- no influence of the parasitic inductances on Vout stage
- Voutput clamping voltage very close to V
BR
(positive strike) and -V
F
(negative strike)
ST1284
Vinput
Voutput
ESD
SURGE
Fig. A4: Measurement conditions
Fig. A5: Remaining voltage at the input and output of the device during a 16kV ESD surge
(IEC61000-4-2).
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