Электронный компонент: ST92F150R1QC

Скачать:  PDF   ZIP

November 2004

1/426

Rev. 4.0

ST92F124/ST92F150/ST92F250

8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM,

E

3

TM

(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD

Memories

� Internal Memory: Single Voltage FLASH up to 256

Kbytes, RAM up to 8Kbytes, 1K byte E

3 TM

(Emulat-

ed EEPROM)

� In-Application Programming (IAP)
� 224 general purpose registers (register file) availa-

ble as RAM, accumulators or index pointers

Clock, Reset and Supply Management

� Register-oriented 8/16 bit CORE with RUN, WFI,

SLOW, HALT and STOP modes

� 0-24 MHz Operation (Int. Clock), 4.5-5.5 V range
� PLL Clock Generator (3-5 MHz crystal)
� Minimum instruction time: 83 ns (24 MHz int. clock)

Up to 80 I/O pins

Interrupt Management

� 4 external fast interrupts + 1 NMI
� Up to 16 pins programmable as wake-up or addition-

al external interrupt with multi-level interrupt handler

DMA controller for reduced processor
overhead

Timers

� 16-bit Timer with 8-bit Prescaler, and Watchdog Tim-

er (activated by software or by hardware)

� 16-bit Standard Timer that can be used to generate

a time base independent of PLL Clock Generator

� Two 16-bit independent Extended Function Timers

(EFTs) with Prescaler, up to two Input Captures and

up to two Output Compares

� Two 16-bit Multifunction Timers, with Prescaler, up

to two Input Captures and up to two Output Com-

pares

Communication Interfaces

� Serial Peripheral Interface (SPI) with Selectable

Master/Slave mode

� One Multiprotocol Serial Communications Interface

with asynchronous and synchronous capabilities

� One asynchronous Serial Communications Interface

with 13-bit LIN Synch Break generation capability

� J1850 Byte Level Protocol Decoder (JBLPD)
� Up to two full I�C multiple Master/Slave Interfaces

supporting Access Bus

� Up to two CAN 2.0B Active interfaces

Analog peripheral (low current coupling)

� 10-bit A/D Converter witvalh up to 16 robust input

channels

Development Tools

� Free High performance Development environment

(IDE) based on Visual Debugger, Assembler, Linker,
and C-Compiler; Real Time Operating System (OS-
EK OS, CMX) and CAN drivers

� Hardware Emulator and Flash Programming Board

for development and ISP Flasher for production

DEVICE SUMMARY

2)

1) see

Section 12.4 on page 406

for important information

2) see

Table 71 on page 403

for the list of supported part numbers

PQFP100

14x20

TQFP64

14x14

TQFP100

14x14

Features

ST92F124R9

ST92F124V1 ST92F150CR9/1 ST92F150CV9/1 ST92F150JDV1

ST92F250CV2

FLASH - bytes

64K

128K

64K/128K

64K/128K

128K

256K

RAM - bytes

2K

4K

2K/4K

2K/4K

6K

8K

E

3 TM

- bytes

1K

1K

1K

1K

1K

1K

Timers and

Serial
Interface

2 MFT, 2 EFT,

STIM, WD,

SCI, SPI, I�C

2 MFT, 2 EFT,

STIM, WD,

2 SCI, SPI, I�C

2 MFT, 2 EFT,

STIM, WD,

SCI, SPI, I�C

2 MFT, 2 EFT,

STIM, WD,

2 SCI, SPI, I�C

2 MFT, 2 EFT,

STIM, WD,

2 SCI, SPI, I�C

2 MFT, 2 EFT,

STIM, WD, 2 SCI,

SPI, 2 I�C

1)

ADC

16 x 10 bits

16 x 10 bits

16 x 10 bits

16 x 10 bits

16 x 10 bits

16 x 10 bits

Network Inter-

face

-

LIN Master

CAN

CAN, LIN Master

2 CAN,J1850,

LIN Master

CAN, LIN Master

Packages

TQFP64

P/TQFP100

TQFP64

P/TQFP100

P/TQFP100

9

2/426

Table of Contents

426

9

1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2

PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3

VOLTAGE REGULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4

I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.5

ALTERNATE FUNCTIONS FOR I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.6

OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2 DEVICE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.1

CORE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.2

MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.3

SYSTEM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.4

MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.5

MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.6

ADDRESS SPACE EXTENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.7

MMU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.8

MMU USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3 SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.3

REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.4

WRITE OPERATION EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.5

PROTECTION STRATEGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.6

FLASH IN-SYSTEM PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.2

MEMORY CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.3

ST92F124/F150/F250 REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.2

INTERRUPT VECTORING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.3

INTERRUPT PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.4

PRIORITY LEVEL ARBITRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.5

ARBITRATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

5.6

EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.7

STANDARD INTERRUPTS (CAN AND SCI-A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.8

TOP LEVEL INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.9

DEDICATED ON-CHIP PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.10 INTERRUPT RESPONSE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.11 INTERRUPT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU) . . . . . . . . . . . . . . . . 112

6 ON-CHIP DIRECT MEMORY ACCESS (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.2

DMA PRIORITY LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

6.3

DMA TRANSACTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.4

DMA CYCLE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

6.5

SWAP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

3/426

Table of Contents

9

6.6

DMA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7 RESET AND CLOCK CONTROL UNIT (RCCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.2

CLOCK CONTROL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.3

CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

7.4

CLOCK CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

7.5

CRYSTAL OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

7.6

RESET/STOP MANAGER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

8 EXTERNAL MEMORY INTERFACE (EXTMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

8.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

8.2

EXTERNAL MEMORY SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

8.3

REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

9.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

9.2

SPECIFIC PORT CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

9.3

PORT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

9.4

INPUT/OUTPUT BIT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

9.5

ALTERNATE FUNCTION ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

9.6

I/O STATUS AFTER WFI, HALT AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

10 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

10.1 TIMER/WATCHDOG (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10.2 STANDARD TIMER (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
10.3 EXTENDED FUNCTION TIMER (EFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
10.4 MULTIFUNCTION TIMER (MFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M) . . . . . . . . . . . 211
10.6 ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A) . . . . . . . . . . . 236
10.7 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
10.8 I2C BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
10.9 J1850 BYTE LEVEL PROTOCOL DECODER (JBLPD) . . . . . . . . . . . . . . . . . . . . . . . . 283
10.10 CONTROLLER AREA NETWORK (BXCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
10.11 10-BIT ANALOG TO DIGITAL CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

11 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
12 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

12.1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.2 VERSION-SPECIFIC SALES CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
12.3 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
12.4 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

13 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

13.1 ST92F124/F150/F250 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
13.2 ST92F150-EMU2 EMULATION CHIP KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . 418

14 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

4/426

ST92F124/F150/F250 - GENERAL DESCRIPTION

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST92F124/F150/F250 microcontroller is de-

veloped and manufactured by STMicroelectronics
using a proprietary n-well HCMOS process. Its
performance derives from the use of a flexible
256-register programming model for ultra-fast con-
text switching and real-time event response. The
intelligent on-chip peripherals offload the ST9 core
from I/O and data management processing tasks
allowing critical application tasks to get the maxi-
mum use of core resources. The new-generation
ST9 MCU devices now also support low power
consumption and low voltage operation for power-
efficient and low-cost embedded systems.

1.1.1 ST9+ Core

The advanced Core consists of the Central
Processing Unit (CPU), the Register File, the Inter-
rupt and DMA controller, and the Memory Man-
agement Unit. The MMU allows a single linear ad-
dress space of up to 4 Mbytes.

Four independent buses are controlled by the
Core: a 22-bit memory bus, an 8-bit register data
bus, an 8-bit register address bus and a 6-bit inter-
rupt/DMA bus which connects the interrupt and
DMA controllers in the on-chip peripherals with the
core.

This multiple bus architecture makes the ST9 fam-
ily devices highly efficient for accessing on and off-
chip memory and fast exchange of data with the
on-chip peripherals.

The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.

The powerful I/O capabilities demanded by micro-
controller applications are fulfilled by the
ST92F150/F124 with 48 (64-pin devices) or 77
(100-pin devices) I/O lines dedicated to digital In-
put/Output and with 80 I/O lines by the ST92F250.
These lines are grouped into up to ten 8-bit I/O
Ports and can be configured on a bit basis under
software control to provide timing, status signals,
an address/data bus for interfacing to the external
memory, timer inputs and outputs, analog inputs,
external interrupts and serial or parallel I/O. Two
memory spaces are available to support this wide
range of configurations: a combined Program/
Data Memory Space and the internal Register File,

which includes the control and status registers of
the on-chip peripherals.

1.1.2 External Memory Interface

100-pin devices have a 22-bit external address
bus allowing them to address up to 4M bytes of ex-
ternal memory.

1.1.3 On-chip Peripherals

Two 16-bit Multifunction Timers, each with an 8 bit
Prescaler and 12 operating modes allow simple
use for complex waveform generation and meas-
urement, PWM functions and many other system
timing functions by the usage of the two associat-
ed DMA channels for each timer.

Two Extended Function Timers provide further
timing and signal generation capabilities.

A Standard Timer can be used to generate a sta-
ble time base independent from the PLL.

An I

2

C interface (two in the ST92F250 device) pro-

vides fast I

2

C and Access Bus support.

The SPI is a synchronous serial interface for Mas-
ter and Slave device communication. It supports
single master and multimaster systems.

A J1850 Byte Level Protocol Decoder is available
(ST92F150JDV1 device only) for communicating
with a J1850 network.

The bxCAN (basic extended) interface (two in the
ST92F150JDV1 device) supports 2.0B Active pro-
tocol. It has 3 transmit mailboxes, 2 independent
receive FIFOs and 8 filters.

In addition, there is an 16 channel Analog to Digital
Converter with integral sample and hold, fast con-
version time and 10-bit resolution.

There is one Multiprotocol Serial Communications
Interface with an integral generator, asynchronous
and synchronous capability (fully programmable
format) and associated address/wake-up option,
plus two DMA channels.

On 100-pin devices, there is an additional asyn-
chronous Serial Communications interface with
13-bit LIN Synch Break generation capability.

Finally, a programmable PLL Clock Generator al-
lows the usage of standard 3 to 5 MHz crystals to
obtain a large range of internal frequencies up to
24 MHz. Low power Run (SLOW), Wait For Inter-
rupt, low power Wait For Interrupt, STOP and
HALT modes are also available.

9

5/426

ST92F124/F150/F250 - GENERAL DESCRIPTION

Figure 1. ST92F124R9: Architectural Block Diagram

256 bytes

Register File

RAM

2 Kbytes

ST9 CORE

8/16 bits

CPU

Interrupt

Management

MEMO

RY B

U

S

RCCU

RE

GISTER

BUS

WATCHDOG

NMI

MISO
MOSI
SCK
SS

ST. TIMER

SPI

SDA
SCL

I

2

C BUS

SCI M

FLASH

64 Kbytes

TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS

WDOUT
HW0SW1

STOUT

Fully

Prog.

I/Os

P0[7:0]
P1[2:0]
P2[7:0]
P3[7:4]
P4[7:4]
P5[7:0]
P6[5:2,0]
P7[7:0]

MF TIMER 0

TINPA0

TOUTA0

TINPB0

TOUTB0

TINPA1

TOUTA1

TINPB1

TOUTB1

INT[5:0]

WKUP[13:0]

MF TIMER 1

E

3 TM

1 Kbyte

OSCIN

OSCOUT

RESET

CLOCK2/8

INTCLK

CK_AF

ADC

AV

DD

AV

SS

AIN[15:8]
EXTRG

V

REG

VOLTAGE

REGULATOR

The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6
and Port7.

ICAPA0

OCMPA0

ICAPB0

ICAPA1

OCMPA1

ICAPB1

EF TIMER 1

EF TIMER 0

9

Document Outline

• 1 GENERAL DESCRIPTION
  • 1.1 INTRODUCTION
    • 1.1.1 ST9+ Core
    • 1.1.2 External Memory Interface
    • 1.1.3 On-chip Peripherals
  • 1.2 PIN DESCRIPTION
    • 1.2.1 I/O Port Alternate Functions
    • 1.2.2 Termination of Unused Pins
  • 1.3 VOLTAGE REGULATOR
  • 1.4 I/O PORTS
  • 1.5 Alternate Functions for I/O Ports
  • 1.6 OPERATING MODES
• 2 DEVICE ARCHITECTURE
  • 2.1 CORE ARCHITECTURE
  • 2.2 MEMORY SPACES
    • 2.2.1 Register File
    • 2.2.2 Register Addressing
  • 2.3 SYSTEM REGISTERS
    • 2.3.1 Central Interrupt Control Register
    • 2.3.2 Flag Register
    • 2.3.3 Register Pointing Techniques
    • 2.3.4 Paged Registers
    • 2.3.5 Mode Register
    • 2.3.6 Stack Pointers
  • 2.4 MEMORY ORGANIZATION
  • 2.5 MEMORY MANAGEMENT UNIT
  • 2.6 ADDRESS SPACE EXTENSION
    • 2.6.1 Addressing 16-Kbyte Pages
    • 2.6.2 Addressing 64-Kbyte Segments
  • 2.7 MMU REGISTERS
    • 2.7.1 DPR[3:0]: Data Page Registers
    • 2.7.2 CSR: Code Segment Register
    • 2.7.3 ISR: Interrupt Segment Register
    • 2.7.4 DMASR: DMA Segment Register
  • 2.8 MMU USAGE
    • 2.8.1 Normal Program Execution
    • 2.8.2 Interrupts
    • 2.8.3 DMA
• 3 SINGLE VOLTAGE FLASH & E3 TM (EMULATED EEPROM)
  • 3.1 INTRODUCTION
  • 3.2 FUNCTIONAL DESCRIPTION
    • 3.2.1 Structure
    • 3.2.2 EEPROM Emulation
    • 3.2.3 Operation
    • 3.2.4 E3 TM Update Operation
    • 3.2.5 Important note on Flash Erase Suspend
  • 3.3 REGISTER DESCRIPTION
    • 3.3.1 Control Registers
    • 3.3.2 Status Registers
  • 3.4 WRITE OPERATION EXAMPLE
  • 3.5 PROTECTION STRATEGY
    • 3.5.1 Non Volatile Registers
    • 3.5.2 Temporary Unprotection
  • 3.6 FLASH IN-SYSTEM PROGRAMMING
    • 3.6.1 Code Update Routine
• 4 REGISTER AND MEMORY MAP
  • 4.1 INTRODUCTION
  • 4.2 MEMORY CONFIGURATION
    • 4.2.1 Reset Vector Location
    • 4.2.2 Location of Vector for External Watchdog Refresh
  • 4.3 ST92F124/F150/F250 REGISTER MAP
• 5 INTERRUPTS
  • 5.1 INTRODUCTION
    • 5.1.1 On-Chip Peripheral Interrupt Sources
  • 5.2 INTERRUPT VECTORING
    • 5.2.1 Divide by Zero trap
    • 5.2.2 Segment Paging During Interrupt Routines
  • 5.3 INTERRUPT PRIORITY LEVELS
  • 5.4 PRIORITY LEVEL ARBITRATION
    • 5.4.1 Priority Level 7 (Lowest)
    • 5.4.2 Maximum Depth of Nesting
    • 5.4.3 Simultaneous Interrupts
    • 5.4.4 Dynamic Priority Level Modification
  • 5.5 ARBITRATION MODES
    • 5.5.1 Concurrent Mode
    • 5.5.2 Nested Mode
  • 5.6 EXTERNAL INTERRUPTS
  • 5.7 STANDARD INTERRUPTS (CAN AND SCI-A)
    • 5.7.1 Functional Description
    • 5.7.2 IMPORTANT NOTE ON STANDARD INTERRUPTS
  • 5.8 TOP LEVEL INTERRUPT
  • 5.9 DEDICATED ON-CHIP PERIPHERAL INTERRUPTS
  • 5.10 INTERRUPT RESPONSE TIME
  • 5.11 INTERRUPT REGISTERS
  • 5.12 WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (WUIMU)
    • 5.12.1 Introduction
    • 5.12.2 Main Features
    • 5.12.3 Functional Description
    • 5.12.4 Programming Considerations
    • 5.12.5 Register Description
    • 5.12.6 Important Note On WUIMU
• 6 ON-CHIP DIRECT MEMORY ACCESS (DMA)
  • 6.1 INTRODUCTION
  • 6.2 DMA PRIORITY LEVELS
  • 6.3 DMA TRANSACTIONS
  • 6.4 DMA CYCLE TIME
  • 6.5 SWAP MODE
  • 6.6 DMA REGISTERS
• 7 RESET AND CLOCK CONTROL UNIT (RCCU)
  • 7.1 INTRODUCTION
  • 7.2 CLOCK CONTROL UNIT
    • 7.2.1 Clock Control Unit Overview
  • 7.3 CLOCK MANAGEMENT
    • 7.3.1 PLL Clock Multiplier Programming
    • 7.3.2 PLL Free Running Mode
    • 7.3.3 CPU Clock Prescaling
    • 7.3.4 Peripheral Clock
    • 7.3.5 Low Power Modes
    • 7.3.6 Interrupt Generation
  • 7.4 CLOCK CONTROL REGISTERS
  • 7.5 CRYSTAL OSCILLATOR
  • 7.6 RESET/STOP MANAGER
    • 7.6.1 Reset Pin Timing
• 8 EXTERNAL MEMORY INTERFACE (EXTMI)
  • 8.1 INTRODUCTION
  • 8.2 EXTERNAL MEMORY SIGNALS
    • 8.2.1 AS: Address Strobe
    • 8.2.2 DS: Data Strobe
    • 8.2.3 RW: Read/Write
    • 8.2.4 DS2: Data Strobe 2
    • 8.2.5 PORT 0
    • 8.2.6 PORT 1
    • 8.2.7 PORT 9 [7:2]
    • 8.2.8 WAIT: External Memory Wait
  • 8.3 REGISTER DESCRIPTION
• 9 I/O PORTS
  • 9.1 INTRODUCTION
  • 9.2 SPECIFIC PORT CONFIGURATIONS
  • 9.3 PORT CONTROL REGISTERS
  • 9.4 INPUT/OUTPUT BIT CONFIGURATION
  • 9.5 ALTERNATE FUNCTION ARCHITECTURE
    • 9.5.1 Pin Declared as I/O
    • 9.5.2 Pin Declared as an Alternate Function Input
    • 9.5.3 Pin Declared as an Alternate Function Output
  • 9.6 I/O STATUS AFTER WFI, HALT AND RESET
• 10 ON-CHIP PERIPHERALS
  • 10.1 TIMER/WATCHDOG (WDT)
    • 10.1.1 Introduction
    • 10.1.2 Functional Description
    • 10.1.3 Watchdog Timer Operation
    • 10.1.4 WDT Interrupts
    • 10.1.5 Register Description
  • 10.2 STANDARD TIMER (STIM)
    • 10.2.1 Introduction
    • 10.2.2 Functional Description
    • 10.2.3 Interrupt Selection
    • 10.2.4 Register Description
  • 10.3 EXTENDED FUNCTION TIMER (EFT)
    • 10.3.1 Introduction
    • 10.3.2 Main Features
    • 10.3.3 Functional Description
    • 10.3.4 Interrupt Management
    • 10.3.5 Register Description
  • 10.4 MULTIFUNCTION TIMER (MFT)
    • 10.4.1 Introduction
    • 10.4.2 Functional Description
    • 10.4.3 Input Pin Assignment
    • 10.4.4 Output Pin Assignment
    • 10.4.5 Interrupt and DMA
    • 10.4.6 Register Description
  • 10.5 MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
    • 10.5.1 Introduction
    • 10.5.2 Main Features
    • 10.5.3 Functional Description
    • 10.5.4 SCI-M Operating Modes
    • 10.5.5 Serial Frame Format
    • 10.5.6 Clocks And Serial Transmission Rates
    • 10.5.7 SCI -M Initialization Procedure
    • 10.5.8 Input Signals
    • 10.5.9 Output Signals
    • 10.5.10 Interrupts and DMA
    • 10.5.11 Register Description
  • 10.6 ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
    • 10.6.1 Introduction
    • 10.6.2 Main Features
    • 10.6.3 General Description
    • 10.6.4 Functional Description
    • 10.6.5 Register Description
    • 10.6.6 Important Notes on SCI-A
  • 10.7 SERIAL PERIPHERAL INTERFACE (SPI)
    • 10.7.1 Introduction
    • 10.7.2 Main Features
    • 10.7.3 General Description
    • 10.7.4 Functional Description
    • 10.7.5 Interrupt Management
    • 10.7.6 Register Description
  • 10.8 I2C BUS INTERFACE
    • 10.8.1 Introduction
    • 10.8.2 Main Features
    • 10.8.3 Functional Description
    • 10.8.4 I2C State Machine
    • 10.8.5 Interrupt Features
    • 10.8.6 DMA Features
    • 10.8.7 Register Description
    • 10.8.8 IMPORTANT NOTES ON I2C
  • 10.9 J1850 Byte Level Protocol Decoder (JBLPD)
    • 10.9.1 Introduction
    • 10.9.2 Main Features
    • 10.9.3 Functional Description
    • 10.9.4 Peripheral Functional Modes
    • 10.9.5 Interrupt Features
    • 10.9.6 DMA Features
    • 10.9.7 Register Description
  • 10.10 CONTROLLER AREA NETWORK (bxCAN)
    • 10.10.1 Introduction
    • 10.10.2 Main Features
    • 10.10.3 General Description
    • 10.10.4 Operating Modes
    • 10.10.5 Functional Description
    • 10.10.6 Interrupts
    • 10.10.7 Register Access Protection
    • 10.10.8 Register Description
    • 10.10.9 IMPORTANT NOTES ON CAN
  • 10.11 10-BIT ANALOG TO DIGITAL CONVERTER (ADC)
    • 10.11.1 Main Characteristics
    • 10.11.2 Introduction
    • 10.11.3 Functional Description
    • 10.11.4 Interrupts
    • 10.11.5 Register Description
• 11 ELECTRICAL CHARACTERISTICS
• 12 GENERAL INFORMATION
  • 12.1 ORDERING INFORMATION
  • 12.2 VERSION-SPECIFIC SALES CONDITIONS
  • 12.3 PACKAGE MECHANICAL DATA
  • 12.4 DEVELOPMENT TOOLS
    • 12.4.1 Socket and Emulator Adapter Information
• 13 KNOWN LIMITATIONS
  • 13.1 ST92F124/F150/F250 KNOWN LIMITATIONS
    • 13.1.1 FLASH ERASE SUSPEND LIMITATIONS
    • 13.1.2 FLASH CORRUPTION WHEN EXITING STOP MODE
    • 13.1.3 I2C LIMITATIONS
    • 13.1.4 SCI-A AND CAN INTERRUPTS
    • 13.1.5 SCI-A MUTE MODE
    • 13.1.6 CAN FIFO CORRUPTION WHEN 2 FIFO MESSAGES ARE PENDING
  • 13.2 ST92F150-EMU2 EMULATION CHIP KNOWN LIMITATIONS
    • 13.2.1 P1 I/O PORT CHARACTERISTICS
    • 13.2.2 RESET BEHAVIOUR FOR BI- DIRECTIONAL, WEAK PULL-UP PORTS
    • 13.2.3 HIGH DRIVE I/OS WHEN BSZ=1
    • 13.2.4 ADC PARASITIC DIODE
    • 13.2.5 ADC ACCURACY VS. NEGATIVE INJECTION CURRENT
    • 13.2.6 I2CECCR REGISTER LIMITATION
    • 13.2.7 I2C BEHAVIOUR DISTURBED DURING DMA TRANSACTIONS
    • 13.2.8 MFT DMA MASK BIT RESET
    • 13.2.9 DMA DATA CORRUPTED BY MFT INPUT CAPTURE
    • 13.2.10 SCI-A WRONG BREAK DURATION
    • 13.2.11 LIN MASTER MODE NOT AVAILABLE ON SCI-A
    • 13.2.12 LIMITATIONS ON TQFP64 DEVICES
• 14 REVISION HISTORY