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ST95040

ST95020, ST95010

4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe

June 1998

1/18

1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE
4.5V to 5.5V for ST950x0
2.5V to 5.5V for ST950x0W
SPI BUS COMPATIBLE SERIAL INTERFACE
2 MHz CLOCK RATE MAX
BLOCK WRITE PROTECTION
STATUS REGISTER
16 BYTE PAGE MODE
WRITE PROTECT
SELF-TIMED PROGRAMMING CYCLE
E.S.D.PROTECTION GREATER than 4000V
SUPPORTS POSITIVE CLOCK SPI MODES

DESCRIPTION
The ST950x0 is a family of Electrically Erasable
Programmable Memories (EEPROM) fabricated
with STMicroelectronics's High Endurance Single
Polysilicon CMOS technology. Each memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).

AI01435B

VCC

ST950x0

HOLD

VSS

Figure 1. Logic Diagram

Serial Clock

Serial Data Input

Serial Data Output

Chip Select

Write Protect

HOLD

Hold

Supply Voltage

Ground

Table 1. Signal Names

SO8 (M)

150mil Width

PSDIP8 (B)

0.25mm Frame

Symbol

Parameter

Value

Unit

Ambient Operating Temperature

40 to 125

STG

Storage Temperature

65 to 150

LEAD

Lead Temperature, Soldering

(SO8 package)
(PSDIP8 package)

40 sec
10 sec

215
260

Output Voltage

0.3 to V

+0.6

Input Voltage with respect to Ground

0.3 to 6.5

Supply Voltage

0.3 to 6.5

ESD

Electrostatic Discharge Voltage (Human Body model)

(2)

4000

Electrostatic Discharge Voltage (Machine model)

(3)

500

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and
other relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500

)

3. EIAJ IC-121 (Condition C) (200pF, 0

)

Table 2. Absolute Maximum Ratings

(1)

The device connected to the bus is selected when
the chip select input (S) goes low. Communications
with the chip can be interrupted with a hold input
(HOLD). The write operation is disabled by a write
protect input (W).
Data is clocked in during the low to high transition
of clock C, data is clocked out during the high to
low transition of clock C.

SIGNALS DESCRIPTION
Serial Output (Q). The output pin is used to trans-
fer data serially out of the Memory. Data is shifted
out on the falling edge of the serial clock.
Serial Input (D). The input pin is used to transfer
data serially into the device. It receivesinstructions,
addresses, and the data to be written. Input is
latched on the rising edge of the serial clock.

VSS

HOLD

VCC

AI01436B

ST950x0

Figure 2A. DIP Pin Connections

AI01437B

VSS

HOLD

VCC

ST950x0

Figure 2B. SO Pin Connections

DESCRIPTION (cont'd)

2/18

ST95040, ST95020, ST95010

AI01438

MSB

LSB

CPHA

D or Q

CPOL

Figure 3. Data and Clock Timing

AI01439B

SPI Interface with

(CPOL, CPHA) =

('0', '0') or ('1', '1')

MICROCONTROLLER

(ST6, ST7, ST9, ST10, OTHERS)

ST95xx0

SCK

SDI

SDO

Figure 4. Microcontroller and SPI Interface Set-up

Serial Clock (C). The serial clock provides the
timing of the serial interface. Instructions, ad-
dresses, or data present at the input pin are latched
on the rising edge of the clock input, while data on
the Q pin changes after the falling edge of the clock
input.
Chip Select (S). When S is high, the Memory is
deselected and the Q output pin is at high imped-
ance and, unless an internal write operation is
underway the Memory will be in the standby power
mode. S low enables the Memory, placing it in the
active power mode. It should be noted that after

power-on, a high to low transition on S is required
prior to the start of any operation.
Write Protect (W). This pin is for hardware write
protection. When W is low, writes to the Memory
are disabled but any other operationsstay enabled.
When W is high, all writes operationsare available.
W going low at any time before the last bit D0 of
the data streamwill reset the write enable latch and
prevent programming. No action on W or on the
write enable latch can interrupt a write cycle which
has commenced.

3/18

ST95040, ST95020, ST95010

Hold (HOLD). The HOLD pin is used to pause
serial communications with the Memory without
resetting the serial sequence. To take the Hold
condition into account, the product must be se-
lected (S = 0). Then the Hold state is validated by
a high to low transition on HOLD when C is low. To
resumethe communications,HOLDis broughthigh
while C is low. During the Hold condition D, Q, and
C are at a high impedance state.

When the Memory is under the Hold condition, it is
possibleto deselect the device. However, the serial
communications will remain paused after a rese-
lect, and the chip will be reset.

The Memory can be driven by a microcontroller with
its SPI peripheral running in either of the two fol-
lowing modes: (CPOL, CPHA) = ('0', '0') or (CPOL,
CPHA) = ('1', '1').

For these two modes, input data is latchedin by the
low to high transition of clock C, and output data is
available from the high to low transition of Clock
(C).

The differencebetween (CPOL, CPHA) = (0, 0) and
(CPOL, CPHA) = (1, 1) is the stand-by polarity: C
remains at '0' for (CPOL, CPHA) = (0, 0) and C
remains at '1'for (CPOL, CPHA) = (1, 1) when there
is no data transfer.

OPERATIONS

All instructions, addresses and data are shifted in
and out of the chip MSB first. Data input (D) is
sampled on the first rising edge of clock (C) after
the chip select (S) goes low. Prior to any operation,
a one-byte instruction code must be entered in the
chip. This code is entered via the data input (D),
and latched on the rising edge of the clock input
(C). To enter an instruction code, the product must
have been previously selected (S = low). Table 3
shows the instruction set and format for device

operation. If an invalid instruction is sent (one not
contained in Table 3), the chip is automatically
deselected. For operations that read or write data
in the memory array, bit 3 of the instruction is the
MSB of the address, otherwise, it is a don't care.

Write Enable (WREN) and Write Disable (WRDI)

The Memory contains a write enable latch. This
latch must be set prior to every WRITE or WRSR
operation. The WREN instruction will set the latch
and the WRDI instruction will reset the latch. The
latch is reset under the following conditions:

W pin is low

Power on

WRDI instruction executed

WRSR instruction executed

WRITE instruction executed

As soon as the WREN or WRDI instruction is
received by the memory, the circuit executes the
instruction and enters a wait mode until it is dese-
lected.

Read Status Register (RDSR)

The RDSR instructionprovidesaccess to the status
register. The status register may be read at any
time, even during a write to the memory operation.
If a Read Status register reaches the 8th bit of the
Status register, an additional 9th clock pulse will
wrap around to read the 1st bit of the Status Reg-
ister

The status register format is as follows:

BP1

BP0

WEL

WIP

BP1, BP0: Read and write bits
WEL, WIP: Read only bits.
b7 to b4: Read only bits.

Instruction

Description

Instruction Format

WREN

Set Write Enable Latch

0000 0110

WRDI

Reset Write Enable Latch

0000 0100

RDSR

Read Status Register

0000 0101

WRSR

Write Status Register

0000 0001

READ

Read Data from Memory Array

0000 A

011

WRITE

Write Data to Memory Array

0000 A

010

Notes: A

= 1, Upper page selected on ST95040.

= 0, Lower page selected on ST95040.

Table 3. Instruction Set

4/18

ST95040, ST95020, ST95010

AI01272

HOLD

Control Logic

High Voltage

Generator

I/O Shift Register

Address Register

and Counter

Data

16 Bytes

X Decoder

Decoder

Block
Protect

Status

Figure 5. Block Diagram

During a write to the memory operation to the
memory array, all bits BP1, BP0, WEL, WIP are
valid and can be read. During a write to the status
register, only the bits WEL and WIP are valid and
can be read. The values of BP1 and BP0 read at
that time correspond to the previouscontents of the
status register.
The Write-In-Process (WIP) read-only bit indicates
whether the Memory is busy with a write operation.

When set to a '1' a write is in progress, when set to
a '0' no write is in progress.
The Write Enable Latch (WEL) read-only bit indi-
cates the status of the write enable latch. When set
to a '1' the latch is set, when set to a '0' the latch is
reset. The Block Protect (BP0 and BP1) bits indi-
cate the extent of the protection employed. These
bits are set by the user issuing the WRSR instruc-
tion. These bits are non-volatile.

5/18

ST95040, ST95020, ST95010

Write Status Register (WRSR)

The WRSR instruction allows the user to select the
size of protected memory. The user may read the
blocks but will be unable to write within the pro-
tected blocks. The blocks and respective WRSR
control bits are shown in Table 4.

When the WRSR instruction and the 8 bits of the
Status Register are latched-in, the internal write
cycle is then triggered by the rising edge of S.

This rising edge of S must appear no later than the
16th clock cycle of the WRSR instruction of the
Status Register content (it must not appear a 17th
clock pulse before the rising edge of S), otherwise
the internal write sequence is not performed.

Read Operation

The chip is first selected by putting S low. The serial
one byte read instruction is followed by a one byte

address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Bit 3 (see Table 3)
of the read instruction contains address bit A8
(most significant address bit). Then the data stored
in the memory at the selected addressis shifted out
on the Q output pin; each bit being shifted out
during the falling edge of the clock (C). The data
stored in the memory at the next address can be
read in sequence by continuing to provide clock
pulses. The byte address is automatically incre-
mented to the next higher address after each byte
of data is shifted out. When the highest address is
reached, the address counter rolls over to 0h allow-
ing the read cycle to be continued indefinitely. The
read operation is terminated by deselecting the
chip. The chip can be deselectedat anytime during
data output. Any read attempt during a write cycle
will be rejected and will deselect the chip.

AI01440

9 10 11 12 13 14 15 16 17 18 19

A6 A5 A4 A3 A2 A1 A0

20 21 22 23

HIGH IMPEDANCE

DATA OUT

INSTRUCTION

BYTE ADDRESS

Figure 6. Read Operation Sequence

Status Register Bits

Protected Block

Array Address Protected

BP1

BP0

ST95040

ST95020

ST95010

none

Upper quarter

180h - 1FFh

C0h - FFh

60h - 7Fh

Upper half

100h - 1FFh

80h - FFh

40h - 7Fh

Whole memory

000h - 1FFh

00h - FFh

00h - 7Fh

Table 4. Write Protected Block Size

Notes:

A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8 is only active on ST95040.

6/18

ST95040, ST95020, ST95010

9 10 11 12 13 14 15 16 17 18 19

A6 A5 A4 A3 A2 A1 A0

20 21 22 23

INSTRUCTION

BYTE ADDRESS

DATA BYTE 1

AI01443

27 28 29 30 31

8+8N

DATA BYTE 16

9+8N

10+8N

11+8N

12+8N

13+8N

14+8N

15+8N

136

137

138

139

140

141

142

143

DATA BYTE N

DATA BYTE 2

Figure 9. Page Write Operation Sequence

9 10 11 12 13 14 15

INSTRUCTION

AI01444

STATUS REG. OUT

HIGH IMPEDANCE

MSB

Figure 10. RDSR: Read Status Register Sequence

Notes:

A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8 is only active on ST95040.

8/18

ST95040, ST95020, ST95010

Byte Write Operation

Prior to any write attempt, the write enable latch
must be set by issuing the WREN instruction. First
the device is selected (S = low) and a serial WREN
instruction byte is issued. Then the product is de-
selected by taking S high. After the WREN instruc-
tion byte is sent, the Memory will set the write
enable latch and then remain in standby until it is
deselected. Then the write state is entered by
selecting the chip, issuing two bytes of instruction
and address, and one byte of data.

Chip Select (S) must remain low for the entire
duration of the operation. The product must be
deselectedjust after the eighth bit of data has been
latched in. If not, the write process is cancelled. As
soon as the product is deselected, the self-timed
write cycle is initiated. While the write isin progress,
the status register may be read to check BP1, BP0,
WEL and WIP. WIP is high during the self-timed
write cycle. When the cycle is completed, the write
enable latch is reset.

Page Write Operation

A maximum of 16 bytes of data may be written
during one non-volatile write cycle. All 16 bytes

must reside on the same page. The page write
mode is the same as the byte write mode except
that instead of deselecting the device after the first
byte of data, up to 15 additionalbytes can be shifted
in prior to deselecting the chip. A page address
begins with address xxxx 0000 and ends with xxxx
1111. If the address counter reaches xxxx 1111and
the clock continues, the counter will roll over to the
first address of the page (xxxx 0000) and overwrite
any previously written data. The programming cy-
cle will only start if the S transition occurs just after
the eighth bit of data of a word is received.

POWER ON STATE

After a Power up the Memory is in the following
state:
The device is in the low power standby state.

The chip is deselected.

The chip is not in hold condition.
The write enable latch is reset.

BP1 and BP0 are unchanged (non-volatile

bits).

AI01445

9 10 11 12 13 14 15

HIGH IMPEDANCE

INSTRUCTION

STATUS REG.

Figure 11. WRSR: Write Status Register Sequence

9/18

ST95040, ST95020, ST95010

DATA PROTECTION AND PROTOCOL SAFETY
All inputs are protected against noise, see Table

Non valid S and HOLD transitions are not taken

into account.

S must come high at the proper clock count in

order to start a non-volatile write cycle (in the
memory array or in the status register), that is
the Chip Select S mustrise during the clock pulse
following the introduction of a multiple of 8 bits.

Access to the memory array during non-volatile

programming cycle is ignored; however, the pro-
gramming cycle continues.

After any of the operations WREN, WRDI, RDSR

is completed, the chip enters a wait state and
waits for a deselect.

The write enable latch is reset upon power-up.
The write enable latch is reset when W is brought

low.

INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state (all data set at all "1's" or FFh).
The block protect bits are initialized to 00.

AI01446

MASTER

ST95xxx

CS3

CS2

CS1

Figure 12. EEPROM and SPI Bus

10/18

ST95040, ST95020, ST95010

AI00825

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Figure 13. AC Testing Input Output Wavef.

Input Rise and Fall Times

50ns

Input Pulse Voltages

0.2V

to 0.8V

Input and Output Timing
Reference Voltages

0.3V

to 0.7V

Output Load

= 100pF

Note that Output Hi-Z is defined as the point where data is no
longer driven.

Table 5. AC Measurement Conditions

Symbol

Parameter

Min

Max

Unit

Input Capacitance (D)

Input Capacitance (other pins)

LPF

Input Signal Pulse Width Filtered Out

Note: 1. Sampled only, not 100% tested.

Table 6. Input Parameters

(1)

= 25

C, f = 2 MHz )

Symbol

Parameter

Test Condition

Min

Max

Unit

Input Leakage Current

Output Leakage Current

Supply Current

C = 0.1 V

/0.9 V

@ 2 MHz, Q = Open

C = 0.1 V

/0.9 V

@ 2 MHz, Q = Open, Note 2

Supply Current (W series)

C = 0.1 V

/0.9 V

@ 1 MHz, V

= 2.5V,

Q = Open

1.5

CC1

Standby Current

S = V

, V

= V

or V

S = V

, V

= V

or V

Note 2

Standby Current (W series)

S = V

, V

= V

or V

= 2.5V

Input Low Voltage

0.3

0.3 V

Input High Voltage

0.7 V

+ 1

(1)

Output Low Voltage

= 2mA

0.4

= 2mA, Note 2

0.4

Output Low Voltage (W series)

= 1.5mA, V

= 2.5V

0.4

(1)

Output High Voltage

= 2mA

0.6

= 2mA, Note 2

0.6

Output High Voltage (W series)

= 0.4mA, V

= 2.5V

0.3

Notes: 1. The device meets output requirements for both TTL and CMOS standards.

2. Test performed at 40 to 125

C temperature range, grade 3.

Table 7. DC Characteristics
(T

= 0 to 70

C, 40 to 85

C or 40 to 125

C; V

= 4.5V to 5.5V or 2.5V to 5.5V)

11/18

ST95040, ST95020, ST95010

Symbol

Alt

Parameter

ST95040 / 020 / 010

Unit

= 4.5V to 5.5V,

= 0 to 70

= 40 to 85

= 4.5V to 5.5V,

= 40 to 125

= 2.5V to 5.5V,

= 0 to 70

= 40 to 85

Min

Max

Min

Max

Min

Max

Clock Frequency

D.C.

MHz

SLCH

CSS

S Active Setup Time

100

200

CHSL

S Not Active Hold
Time

100

200

(1)

CLH

Clock High Time

190

200

400

(1)

CLL

Clock Low Time

200

400

CLCH

Clock Rise Time

CHCL

Clock Fall Time

DVCH

DSU

Data In Setup Time

100

CHDX

Data In Hold Time

100

DLDH

Data In Rise Time

DHDL

Data In Fall Time

HHCH

HSU

HOLD Setup Time

100

200

HLCH

Clock Low Hold Time

200

CLHL

HOLD Hold Time

200

CLHH

Clock Low Set-up
Time

100

200

CHSH

S Active Hold Time

200

SHCH

S Not Active Setup
Time

100

200

SHSL

CSH

S Deselect Time

200

SHQZ

DIS

Output Disable Time

150

200

CLQV

Clock Low to Output
Valid

240

300

400

CLQX

Output Hold Time

QLQH

(2)

Output Rise Time

100

200

QHQL

(2)

Output Fall Time

100

200

HHQX

HOLD High to Output
Low-Z

100

200

HLQZ

HOLD Low to Output
High-Z

130

200

Write Cycle Time

Notes: 1. t

+ t

1/fc

2. Value guaranteed by characterization, not 100% tested in production.

Table 8. AC Characteristics

12/18

ST95040, ST95020, ST95010

ORDERING INFORMATION SCHEME

Notes: 1. Data In is strobed on rising edge of the clock (C) and Data Out is synchronized from the falling edge of the clock.

2. Temperature range on request only, 5V

10% only.

Devices are shipped from the factory with the memory content set at all "1's" (FFh).

For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the STMicroelectronics Sales Office nearest to you.

Density

4K (512 x 8)

2K (256 x 8)

1K (128 x 8)

Data Strobe

Note 1

Operating Voltage

blank 4.5V to 5.5V

2.5V to 5.5V

Package

PSDIP8
0.25 mm Frame

SO8
150mils Width

Option

Tape & Reel
Packing

Temperature Range

0 to 70

40 to 85

(2)

40 to 125

Example:

ST95xx0

15/18

ST95040, ST95020, ST95010

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

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18/18

ST95040, ST95020, ST95010

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