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April 2005
STE45NK80ZD
N-CHANNEL 800V - 0.11
- 45 A ISOTOP
Super FREDMeshTM MOSFET
Table 1: General Features
s
TYPICAL R
DS
(on) = 0.11
s
EXTREMELY HIGH dv/dt CAPABILITY
s
100% AVALANCHE TESTED
s
GATE CHARGE MINIMIZED
s
VERY LOW INTRINSIC CAPACITANCES
s
VERY GOOD MANUFACTURING
REPEATIBILITY
DESCRIPTION
The SuperFREDMeshTM series is obtained
through an extreme optimization of ST's well es-
tablished strip-based PowerMESHTM layout. In ad-
dition to pushing on-resistance significantly down,
special care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs including revolutionary MD-
meshTM products.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
IDEAL FOR WELDING EQUIPMENT
Table 2: Order Codes
Figure 1: Package
Figure 2: Internal Schematic Diagram
TYPE
V
DSS
R
DS(on)
I
D
Pw
STE45NK80ZD
800 V
< 0.13
45 A
600 W
ISOTOP
SALES TYPE
MARKING
PACKAGE
PACKAGING
STE45NK80ZD
E45NK80ZD
ISOTOP
TUBE
Rev. 6
STE45NK80ZD
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Table 3: Absolute Maximum ratings
(*)
Pulse width limited by safe operating area
(1) I
SD
45A, di/dt
500 A/s, V
DD
V
(BR)DSS.
Table 4: Thermal Data
Table 5: Avalanche Characteristics
Table 6: Gate-Source Zener Diode
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the
usage of external components.
Symbol
Parameter
Value
Unit
V
DS
Drain-source Voltage (V
GS
= 0)
800
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
800
V
V
GS
Gate- source Voltage
30
V
I
D
Drain Current (continuous) at T
C
= 25C (Steady State)
Drain Current (continuous) at T
C
= 100C
45
28
A
A
I
DM
(*)
Drain Current (pulsed)
180
A
P
TOT
Total Dissipation at T
C
= 25C (Steady State)
600
W
P
TOT
Derating Factor
5
W/C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5k
)
7
KV
dv/dt (1)
Peak Diode Recovery voltage slope
8
V/ns
V
ISO
Insulation Withstand Voltage (AC-RMS) from All Four
Terminals to External Heatsink
2500
V
T
j
Tstg
Operating Junction Temperature
Storage Temperature
- 65 to 150
C
Rthj-case
Thermal Resistance Junction-case Max
0.2
C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
40
C/W
Symbol
Parameter
Max. Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
45
A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 C, I
D
= I
AR
, V
DD
= 35 V)
1.2
J
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
BV
GSO
Gate-Source Breakdown
Voltage
Igs= 1mA (Open Drain)
30
V
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STE45NK80ZD
ELECTRICAL CHARACTERISTICS (T
CASE
=25C UNLESS OTHERWISE SPECIFIED)
Table 7: On/Off
Table 8: Dynamic
Table 9: Source Drain Diode
(1) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
(2) Pulse width limited by safe operating area.
(3) C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 1 mA, V
GS
= 0
800
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 C
10
100
A
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= 20V
10
A
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 150A
2.5
3.75
4.5
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, I
D
= 22.5 A
0.11
0.13
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs
(1)
Forward Transconductance
V
DS
= 15V
,
I
D
= 22.5 A
35
S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0
26000
1620
260
pF
pF
pF
C
oss eq.
(3)
Equivalent Output
Capacitance
V
GS
= 0V, V
DS
= 0V to 720V
700
pF
t
d(on)
t
r
t
d(off)
t
f
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
V
DD
= 400 V, I
D
= 20 A
R
G
= 4.7
,V
GS
= 10 V
(see Figure 17)
105
128
350
174
ns
ns
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 400 V, I
D
= 40 A,
V
GS
= 10V
558
121
307
781
nC
nC
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
I
SDM
(2)
Source-drain Current
Source-drain Current (pulsed)
45
180
A
A
V
SD
(1)
Forward On Voltage
I
SD
= 45 A, V
GS
= 0
1.6
V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 40 A, di/dt = 100A/s
V
DD
= 50 V, T
j
= 25C
(see Figure 18)
375
4.65
24.8
ns
C
A
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 40 A, di/dt = 100A/s
V
DD
= 50 V, T
j
= 150C
(see Figure 18)
568
9.66
34
ns
C
A
STE45NK80ZD
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Figure 3: Safe Operating Area
Figure 4: Output Characteristics
Figure 5: Transconductance
Figure 6: Thermal Impedance
Figure 7: Transfer Characteristics
Figure 8: Static Drain-source On Resistance
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STE45NK80ZD
Figure 9: Gate Charge vs Gate-source Voltage
Figure 10: Normalized Gate Thereshold Volt-
age vs Temperature
Figure 11: Source-Drain Diode Forward Char-
acteristics
Figure 12: Capacitance Variations
Figure 13: Normalized On Resistance vs Tem-
perature
Figure 14: Normalized BVdss vs Temperature
STE45NK80ZD
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Figure 15: Avalanche Energy vs Starting Tj
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STE45NK80ZD
Figure 16: Unclamped Inductive Load Test Cir-
cuit
Figure 17: Switching Times Test Circuit For
Resistive Load
Figure 18: Test Circuit For Inductive Load
Switching and Diode Recovery Times
Figure 19: Unclamped Inductive Wafeform
Figure 20: Gate Charge Test Circuit
STE45NK80ZD
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DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
11.8
12.2
0.466
0.480
B
8.9
9.1
0.350
0.358
C
1.95
2.05
0.076
0.080
D
0.75
0.85
0.029
0.033
E
12.6
12.8
0.496
0.503
F
25.15
25.5
0.990
1.003
G
31.5
31.7
1.240
1.248
H
4
0.157
J
4.1
4.3
0.161
0.169
K
14.9
15.1
0.586
0.594
L
30.1
30.3
1.185
1.193
M
37.8
38.2
1.488
1.503
N
4
0.157
O
7.8
8.2
0.307
0.322
B
E
H
O
N
J
K
L
M
F
A
C
G
D
ISOTOP MECHANICAL DATA
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STE45NK80ZD
Table 10: Revision History
Date
Revision
Description of Changes
05-Jul-2004
1
First Release.
15-Oct-2004
2
New value inserted in table 3. (V
ISO
)
04-Nov-2004
3
Preliminary Status
09-Dec-2004
4
Final datasheet
14-Dec-2004
5
Modified note 1 in table3.
05-Apr-2055
6
Modified figure 12
STE45NK80ZD
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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