MONOCHIP SLIC OPTIMISED FOR WLL &
ISDN-TA APPLICATIONS
IMPLEMENT ALL KEY FEATURES OF THE
BORSHT FUNCTION
SINGLE SUPPLY (5.5 TO 15.8V)
BUILT IN DC/DC CONVERTER CONTROL-
LER.
SOFT BATTERY REVERSAL WITH PRO-
GRAMMABLE TRANSITION TIME.
ON-HOOK TRANSMISSION.
PROGRAMMABLE OFF-HOOK DETECTOR
THRESHOLD
METERING PULSE GENERATION AND FIL-
TER
INTEGRATED RINGING
INTEGRATED RING TRIP
PARALLEL CONTROL INTERFACE (3.3V
LOGIC LEVEL)
PROGRAMMABLE CONSTANT CURRENT
FEED
SURFACE MOUNT PACKAGE
INTEGRATED THERMAL PROTECTION
-40 TO +85
C OPERATING RANGE
DESCRIPTION
The STLC3055 is a SLIC device specifically de-
signed for WLL (Wireless Local Loop) and ISDN-
Terminal Adaptors. One of the distinctive charac-
teristic of this device is the ability to operate with
a single supply voltage (from +5.5V to +15.8V)
and self generate the negative battery by means
of an on chip DC/DC converter controller that
drives an external MOS switch.
The battery level is properly adjusted depending
on the operating mode. A useful characteristic for
October 1999
D0
D1
D2
DET
RTTX
CAC
ILTF RD IREF RLIM RTH
CSVR
CVCC
VPOS
BGND
TIP
RING
VBAT
AGND
TX
RX
ZAC1
ZAC
RS
ZB
CTTX1
CTTX2
FTTX
CKTTX
SUPERVISION
TTX PROC
AC PROC
REFERENCE
STAGE
LINE
DR IVER
CR EV
INPUT LOGICAND DECODER
OUTPUT LOGIC
VOLT.
Vcc
Vss
Agnd
OUTPUT
REG.
Status and functions
CLK
R SENSE
GATE
VF
DC/DC
CONV.
DC PROC
Vba t
BLOCK DIAGRAM
TQFP44
ORDERING NUMBERS: STLC3055Q
STLC3055QTR
STLC3055
WLL & ISDN-TA SUBSCRIBER LINE INTERFACE CIRCUIT
1/22
these applications is the integrated ringing gener-
ator.
The control interface is a parallel type with open
drain output and 3.3V logic levels.
The metering pulses are generated on chip start-
ing from two logic signals (0, 3.3V) one define the
metering pulse frequency and the other the me-
tering pulse duration. An on chip circuit then pro-
vides the proper shaping and filtering. Metering
pulse amplitude and shaping (rising and decay
time) can be programmed by external compo-
nents. A dedicated cancellation circuit avoid pos-
sible CODEC input saturation due to Metering
pulse echo.
Constant current feed can be set from 20mA to
40mA. Off-hook detection threshold is program-
mable from 5mA to 9mA.
The device, developed in BCD100II technology
(100V process), operates in the extended tem-
perature range and integrates a thermal protec-
tion that sets the device in power down when Tj
exceeds 140
C.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
pos
Positive Supply Voltage
-0.4 to +17
V
A/BGND
AGND to BGND
-1 to +1
V
V
dig
Pin D0, D1, D2, DET, CKTTX
-0.4 to 5.5
V
T
j
Max. junction Temperature
150
C
V
btot
(1)
Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device
supply pins).
100
V
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.
RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)
1
2
3
5
6
4
7
8
9
10
17
11
18
19
20
21
22
44
43
42
41
39
40
38
37
36
35
34
28
27
26
24
23
25
33
32
31
29
30
N.C.
RES
PD
D1
D0
D2
CTTX2
CTTX1
CKTTX
N.C.
DET
RTTX
FTTX
RX
ZAC1
RS
ZAC
ZB
CAC
TX
VF
CLK
VBAT1
CREV
N.C.
TIP
N.C.
N.C.
N.C.
RING
N.C.
VBAT
BGND
RLIM
AGND
CVCC
RSENSE
GATE
VPOS
CSVR
ILTF
RD
IREF
RTH
D97TL279A
12
13
14
15
16
PIN CONNECTION
DESCRIPTION (continued)
STLC3055
2/22
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction to Ambient
Typ.
60
C/W
PIN DESCRIPTION
N.
Name
Function
25
VPOS
Positive supply input ranging from 5.5V to 15.8V.
34
BGND
Battery Ground, must be shorted with AGND.
27
AGND
Analog Ground, must be shorted with BGND.
16
ZAC
AC impedance synthesis.
15
ZAC1
RX buffer output, the AC impedance is connected from this node to ZAC.
17
RS
Protection resistors image (the image resistor is connected from this node to ZAC).
18
ZB
Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from this
node to AGND. ZA impedance is connected from this node to ZAC1).
20
TX
4 wire output port (TX output). The signal is referred to AGND. If connected to single supply
CODEC input it must be DC decoupled with proper capacitor.
14
RX
4 wire input port (RX input); 300K
input impedance. This signal is referred to AGND. If
connected to single supply CODEC output it must be DC decoupled with proper capacitor.
19
CAC
AC feedback input, AC/DC split capacitor (CAC).
32
ILTF
Transversal line current image output.
41
TIP
2 wire port; TIP wire (Ia is the current sourced from this pin).
37
RING
2 wire port; RING wire (Ib is the current sunk into this pin).
28
RLIM
Constant current feed programming pin (via RLIM). RLIM should be connected close to this
pin and PCB layout should avoid noise injection on this pin.
30
RTH
Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin
and PCB layout should avoid noise injection on this pin.
29
IREF
Internal bias current setting pin. RREF should be connected close to this pin and PCB layout
should avoid noise injection on this pin.
43
CREV
Reverse polarity transition time control. One proper capacitor connected between this pin and
AGND is setting the reverse polarity transition time. This is the same transition time used to
shape the "trapezoidal ringing" during ringing injection.
31
RD
DC feedback and ring trip input. RD should be connected close to this pin and PCB layout
should avoid noise injection on this pin.
OPERATING RANGE
Symbol
Parameter
Value
Unit
V
pos
Positive Supply Voltage
5.5 to +15.8
V
A/BGND
AGND to BGND
-100 to +100
V
V
dig
Pin D0, D1, D2, DET, CKTTX, PD
-0.25 to 5.25
V
T
op
Ambient Operating Temperature Range
-40 to +85
C
V
bat
(1)
Self Generated Battery Voltage
-74 max.
V
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.
RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)
STLC3055
3/22
FUNCTIONAL DESCRIPTION
The STLC3055 is a device specifically developed
for WLL and ISDN-TA applications.
It is based on a SLIC core, on purpose optimised
for these applications, with the addition of a
DC/DC converter controller to fulfil the WLL and
ISDN-TA design requirements.
The SLIC performs the standard feeding, signal-
ling and transmission functions.
It can be set in three different operating modes
via the D0, D1, D2 pins of the control logic inter-
face (0 to 3.3V logic levels). The loop status is
carried out on the DET pin (active low).
The DET pin is an open drain output to allow easy
interfacing with both 3.3V and 5V logic levels.
The four possible SLIC's operating modes are:
Power Down
High Impedance Feeding (HI-Z)
Active
Ringing
Table 1 shows how to set the different SLIC oper-
ating modes.
Table 1. SLIC operating modes.
PD
D0
D1
D2
Operating Mode
0
0
0
X
Power Down
1
0
0
X
H.I. Feeding (HI-Z)
1
0
1
0
Active Normal Polarity
1
0
1
1
Active Reverse Polarity
1
1
1
0
Active TTX injection (N.P.)
1
1
1
1
Active TTX injection (R.P.)
1
1
0
0/1
Ring (D2 bit toggles @ fring)
N.
Name
Function
4
PD
Power Down input. Normally connected to CVCC (or to logic level high). Can be used to set
TIP and Ring terminals in open circuit setting PD=0 and D0=D1=0.
26
CVCC
Internal positive voltage supply filter.
35
VBAT
Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted
to VBAT1.
23
GATE
Driver for external Power MOS transistor.
21
VF
Feedback input for DC/DC converter controller.
22
CLK
Power Switch Controller Clock (typ. 125KHz). From version marked STLC3055 A5, this pin
can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an
internal auto-oscillation is internally generated and it is used instead of the external clock.
When the CLK pin is connected to AGND, the GATE output is disabled.
24
RSENSE
Voltage input for current sensing. RSENSE should be connected close to this pin and VPOS
pin. The PCB layout should minimize the extra resistance introduced by the copper tracks.
1
D0
Control Interface: input bit 0.
2
D1
Control Interface: input bit 1.
3
D2
Control interface: input bit 2.
8
DET
Logic interface output of the supervision detector (active low).
33
CSVR
Battery supply filter capacitor.
12
RTTX
Metering pulse cancellation buffer output. TTX filter network should be connected to this point.
If not used should be left open.
13
FTTX
Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering.
10
CTTX1
Metering burst shaping external capacitor.
11
CTTX2
Metering burst shaping external capacitor.
9
CKTTX
Metering pulse clock input (12 KHz or 16KHz square wave).
44
VBAT1
Frame connection. Must be shorted to VBAT.
5
RES
Reserved, must be connected to AGND.
6, 7,36,
38,39,
40,42
NC
Not connected.
PIN DESCRIPTION (continued)
STLC3055
4/22
The DC/DC converter controller is driving an ex-
ternal power MOS transistor (P-Channel) in order
to generate the negative battery voltage needed
for device operation.
The DC/DC converter controller is synchronised
with an external CLK (125KHZ typ.).
From version marked STLC3055 A5, it can be
synchronised to an internal clock generated when
the pin CLK is connected to CVCC. One sensing
resistor in series to Vpos supply allows to fix the
maximum allowed input peak current. This feature
is implemented in order to avoid overload on
Vpos supply in case of line transient (ex. ring trip
detection).
The typical value is obtained for a sensing resis-
tor equal to 110m
that will guarantee an aver-
age current consumption from Vpos < 700mA.
When in on-hook the self generated battery volt-
age is set to a predefined value.
This value can be adjusted via one external resis-
tor (RF1) and it is typical -50V. When RING mode
is selected this value is increased to -70V typ.
Once the line goes in off-hook condition, the
DC/DC converter automatically adjust the gener-
ated battery voltage in order to feed the line with
a fixed DC current (programmable via RLIM) opti-
mising in this way the power dissipation.
OPERATING MODES
Power Down
DC CHARACTERISTIC & SUPERVISION
When this mode is selected the SLIC is switched
off and the TIP and RING pins are in high imped-
ance. Also the line detectors are disabled there-
fore the off-hook condition cannot be detected.
This mode can be selected in emergency condi-
tion when it is necessary to cut any current deliv-
ered to the line.
This mode is also forced by STLC3055 in case of
thermal overload (Tj > 140
C).
In this case the device goes back to the previous
status as soon as the junction temperature de-
crease under the hysteresis threshold.
AC CHARACTERISTICS
The 2W port is set in high impedance, the TX
output buffer is a low impedance output, no AC
transmission is possible.
High Impedance Feeding (HI-Z)
DC CHARACTERISTIC & SUPERVISION
This operating mode is normally selected when
the telephone is in on-hook in order to monitor the
line status keeping the power consumption at the
minimum.
The output voltage in on-hook condition is equal
to the self generated battery voltage (-50V typ).
When off-hook occurs the DET becomes active
(low logic level).
The off-hook threshold in HI-Z mode is the same
value as programmed in ACTIVE mode.
The DC characteristic in HI-Z mode is just equal
to the self generated battery with 2x(1500W+Rp)
in series (see fig.1), where Rp is the external pro-
tection resistance.
AC CHARACTERISTICS
The AC impedance shown at the 2W port
(TIP/RING) is the same as the DC
one. The
TIP/RING AC impedance will be 2x(1500
+ Rp)
or high impedance.
Active
DC CHARACTERISTICS & SUPERVISION
When this mode is selected the STLC3055 pro-
vides both DC feeding and AC transmission.
The STLC3055 feeds the line with a constant cur-
rent fixed by RLIM (20mA to 40mA range). The
on-hook voltage is typically 40V allowing on-hook
transmission; the self generated Vbat is -50V typ.
If the loop resistance is very high and
the line
current cannot reach the programmed constant
current feed value, the STLC3055 behaves like a
40V voltage source with a series impedance
equal to the protection resistors 2xRp (typ.
2x41
) plus the internal resistance. Fig. 2 shows
the typical DC characteristic in ACTIVE mode.
Vbat
IL
VL
Vbat (-50V)
2x(R1+Rp)
Slope: 2x(R1+Rp)
(R1=1500ohm)
Figure 1. DC Characteristic in HI-Z Mode.
STLC3055
5/22
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