MONOCHIP SLIC OPTIMISED FOR WLL AP-
PLICATIONS
IMPLEMENT ALL KEY FEATURES OF THE
BORSHT FUNCTION
SINGLE SUPPLY (5.5 TO 15.8V)
BUILT IN DC/DC CONVERTER CONTROL-
LER.
SOFT BATTERY REVERSAL WITH PRO-
GRAMMABLE TRANSITION TIME.
ON-HOOK TRANSMISSION.
PROGRAMMABLE OFF-HOOK DETECTOR
THRESHOLD
METERING PULSE GENERATION AND FIL-
TER
INTEGRATED RINGING
INTEGRATED RING TRIP
DUAL 2W PORT FOR DATA/VOICE OPERA-
TION
PARALLEL CONTROL INTERFACE (3.3V
LOGIC LEVEL)
PROGRAMMABLE CONSTANT CURRENT
FEEDER
SURFACE MOUNT PACKAGE
INTEGRATED THERMAL PROTECTION
-40 TO +85
C OPERATING RANGE
DESCRIPTION
The STLC3065 is a SLIC device specifically de-
signed for WLL (Wireless Local Loop) application.
One of the distinctive characteristics of this de-
vice is the ability to operate with a single supply
voltage (from +5.5V to +15.8V) and self generate
the negative battery by means of an on chip
DC/DC converter controller that drives an external
October 1999
D0
D1
D2
P1
P2
DET DET1
DET2
RTTX
CAC
ILTF R D IREF RLIM RTH
CSVR
CVCC
VPOS
BGND
TIP1
R ING1
TIP2
RING2
VBAT
AGND
TX
R X
ZAC1
ZAC
R S
ZB
C TTX1
CTTX2
FTTX
CKTTX
SUPERVISION
TTX PROC
AC PROC
REFERENCE
SWITCH
LINE
D RIVER
C REV
IN PUT LOGIC AND DECODER
OUTPUT LOGIC
VOLT.
Vcc
Vss
Agnd
LINE
REG.
Status and functions
C LK
R SENSE
GATE
VF
DC/DC
CONV.
DC PROC
Vbat
BLOCK DIAGRAM
TQFP44
ORDERING NUMBERS: STLC3065Q
STLC3065QTR
STLC3065
WLL SUBSCRIBER LINE INTERFACE CIRCUIT
1/27
MOS switch.
The self generated battery voltage tracks the line
resistance. In this way the power dissipation in-
side the device is low enough to allow the use of
small SMD package (TQFP44).
Other useful characteristics for application in the
WLL environment are the integrated ringing gen-
erator and the dual two wire port that allows to
drive two different terminal equipment whether
the transmission is voice or data. When one port
is transmitting the other one is idle.
The control interface is a parallel type with open
drain output and 3.3V logic levels.
The metering pulses are generated on chip start-
ing from two logic signals (0, 3.3V) one defines
the metering pulse frequency and the other the
metering pulse duration. An on chip circuit then
provides the proper shaping and filtering.
Metering pulse amplitude and shaping (rising and
decay time) can be programmed by external com-
ponents. A dedicated cancellation circuit avoid
possible CODEC input saturation due to Metering
pulse echo.
Constant current feed can be set from 20mA to
40mA.
Off-hook detection threshold is programmable
from 5mA to 9mA.
The device, developed in BCD100II technology
(100V process), operates in the extended tem-
perature range and integrates a thermal protec-
tion that set the device in power down when Tj
exceeds 140
C.
1
2
3
5
6
4
7
8
9
10
17
11
18
19
20
21
22
44
43
42
41
39
40
38
37
36
35
34
28
27
26
24
23
25
33
32
31
29
30
DET1
P2
P1
D1
D0
D2
CTTX2
CTTX1
CKTTX
DET2
DET
RTTX
FTTX
RX
ZAC1
RS
ZAC
ZB
CAC
TX
VF
CLK
VBAT1
CREV
TIP2
TIP1
N.C.
N.C.
N.C.
RING1
RING2
VBAT
BGND
RLIM
AGND
CVCC
RSENSE
GATE
VPOS
CSVR
ILTF
RD
IREF
RTH
D96TL273B
12
13
14
15
16
PIN CONNECTION
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
pos
Positive Supply Voltage
-0.4 to +17
V
A/BGND
AGND to BGND
-1 to +1
V
V
dig
Pin D0, D1, D2, P1, P2, DET, DET1, DET2 CKTTX
-0.4 to 5.5
V
T
j
Max. junction Temperature
150
C
V
btot
(1)
Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device
supply pins).
100
V
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.
RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 13)
DESCRIPTION (continued)
STLC3065
2/27
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction to Ambient
Typ.
60
C/W
PIN DESCRIPTION
N.
Name
Function
25
VPOS
Positive supply input ranging from 5.5V to 15.8V.
34
BGND
Battery Ground, must be shorted with AGND.
27
AGND
Analog Ground, must be shorted with BGND.
16
ZAC
AC impedance synthesis.
15
ZAC1
RX buffer output, the AC impedance is connected from this node to ZAC.
17
RS
Protection resistors image (the image resistor is connected from this node to ZAC).
18
ZB
Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from this
node to AGND. ZA impedance is connected from this node to ZAC1).
20
TX
4 wire output port (TX output). The signal is referred to AGND. If connected to single supply
CODEC input it must be DC decoupled with proper capacitor.
14
RX
4 wire input port (RX input); 300K
input impedance. This signal is referred to AGND. If
connected to single supply CODEC output it must be DC decoupled with proper capacitor.
19
CAC
AC feedback input, AC/DC split capacitor (CAC).
32
ILTF
Transversal line current image output.
41
TIP1
2 wire port #1; TIP wire (Ia is the current sourced from this pin).
37
RING1
2 wire port #1; RING wire (Ib is the current sunk into this pin).
42
TIP2
2 wire port #2; TIP wire (Ia is the current sourced from this pin)
36
RING2
2 wire port #2; RING wire (Ib is the current sunk into this pin)
28
RLIM
Constant current feed programming pin (via RLIM). RLIM should be connected close to this
pin and PCB layout should avoid noise injection on this pin.
30
RTH
Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin
and PCB layout should avoid noise injection on this pin.
29
IREF
Internal bias current setting pin. RREF should be connected close to this pin and PCB layout
should avoid noise injection on this pin.
43
CREV
Reverse polarity transition time control. One proper capacitor connected between this pin and
AGND is setting the reverse polarity transition time. This is the same transition time used to
shape the "trapezoidal ringing" during ringing injection.
26
CVCC
Internal positive voltage supply filter.
OPERATING RANGE
Symbol
Parameter
Value
Unit
V
pos
Positive Supply Voltage
5.5 to +15.8
V
A/BGND
AGND to BGND
-100 to +100
V
V
dig
Pin D0, D1, D2, DET, DET1, DET2, CKTTX, P
1
, P
2
-0.25 to 5.25
V
T
op
Ambient Operating Temperature Range
-40 to +85
C
V
bat
(1)
Self Generated Battery Voltage
-74 max.
V
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2.
RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)
STLC3065
3/27
FUNCTIONAL DESCRIPTION
The STLC3065 is a device specifically developed
for WLL application.
It is based on a SLIC core, on purpose optimised
for this application, with the addition of a DC/DC
converter controller and a dual port in order to ful-
fil the WLL requirements.
The SLIC core performs the standard feeding,
signalling and transmission functions.
It can be set in three different operating modes
via the D0, D1, D2 pins of the control logic inter-
face (0 to 3.3V logic levels). The loop status is
carried out on the DET pin (active low).The DET
pin is an open drain output to allow easy interfac-
ing with both 3.3V and 5V logic levels.
The three possible SLIC core operating modes
are:
Power Down (PWD)
Active
Ringing
Table 1 shows how to set the different SLIC core
operating modes.
Table 1. SLIC core operating modes.
D0
D1
D2
Operating Mode
0
0
X
Power Down
0
1
0
Active Normal Polarity
0
1
1
Active Reverse Polarity
1
1
0
Active TTX injection (N.P.)
1
1
1
Active TTX injection (R.P.)
1
0
0/1
Ring (D2 bit toggles @ fring)
N.
Name
Function
35
VBAT
Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted
to VBAT1.
23
GATE
Driver for external Power MOS transistor.
21
VF
Feedback input for DC/DC converter controller.
22
CLK
Power Switch Controller Clock (typ. 125KHz). From version marked STLC3065 A5, this pin
can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an
internal auto-oscillation is internally generated and it is used instead of the external clock.
When the CLK pin is connected to AGND, the GATE output is disabled.
24
RSENSE
Voltage input for current sensing. RSENSE should be connected close to this pin and VPOS
pin. The PCB layout should minimize the extra resistance introduced by the copper tracks.
1
D0
Control Interface: input bit 0.
2
D1
Control Interface: input bit 1.
3
D2
Control interface: input bit 2.
4
P1
Control Interface: port 1 selection bit
5
P2
Control Interface: port 2 selection bit
8
DET
Logic interface output of the supervision detector (active low).
6
DET1
Logic interface output of thr linr port 1 detector (active low)
7
DET2
Logic interface output of thr linr port 2 detector (active low)
33
CSVR
Battery supply filter capacitor.
12
RTTX
Metering pulse cancellation buffer output. TTX filter network should be connected to this point.
If not used should be left open.
13
FTTX
Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering.
10
CTTX1
Metering burst shaping external capacitor.
11
CTTX2
Metering burst shaping external capacitor.
9
CKTTX
Metering pulse clock input (12 KHz or 16KHz square wave).
44
VBAT1
Frame connection. Must be shorted to VBAT.
38,39,
40
NC
Not connected.
PIN DESCRIPTION (continued)
STLC3065
4/27
The STLC3065 operating modes will be obtained
as combination of the SLIC core status and the
dual port configuration.
The DC/DC converter controller is driving an ex-
ternal power MOS transistor (P-Channel) in order
to generate the negative battery voltage needed
for device operation.
The DC/DC converter controller is synchronised
with an external CLK (125KHz typ.).
From version marked STLC3065 A5, it can be
synchronised to an internal clock generated when
the pin CLK is connected to CVCC. One sensing
resistor in series to Vpos supply allows to fix the
maximum allowed input peak current. This feature
is implemented in order to avoid overload on
Vpos supply in case of line transient (ex. ring trip
detection).
The typical value is obtained for a sensing resis-
tor equal to 110m
that will guarantee an aver-
age current consumption from Vpos < 700mA.
In on-hook condition the self generated battery
voltage is set to a predefined value.
This value can be adjusted via one external resis-
tor (RF1) and it is typical -50V. When RING mode
is selected this value is increased up to -70V typ.
Once the line goes in off-hook condition the
DC/DC converter automatically adjust the gener-
ated battery voltage in order to feed the line with
a fixed DC current (programmable via RLIM) opti-
mising in this way the power dissipation.
The Dual Port allows to connect the SLIC core to
one of the two possible 2W ports (TIP1/RING1,
TIP2/RING2).
Dual port concept
One switches array integrated in STLC3065 al-
lows to connect the TIP and RING output of the
SLIC core to one of the two 2W
ports
(TIP1/RING1 or TIP2/RING2). For special condi-
tions it is also possible to connect both ports to
the SLIC core.The structure of the switches array
is shown in fig.1 and it is controlled via the two
logic inputs P1 and P2.
Depending on the switches configurations each
2W port (TIP1/RING1 or TIP2/RING2) can be set
in four possible conditions:
Open
Connected to BGND and Battery via two inte-
grated 1.5K
resistors.
Connected to the SLIC core
Connected to an internal 300
A (min.) current
source.
Depending on the SLIC core operating modes
(defined by D0,D1 and D2) only a subset of these
conditions can be programmed.
SLIC core
DC/DC converter
controller
Tip1
Ring1
Ring2
Tip2
TX
RX
CONTROL
INTERFACE
SW3T
SW5R
SW6R
SW4T
SW1T
SW1T
SW2R
SW2T
SW3R
300
A
SW4R
300
A
FUNCTIONAL DIAGRAM
STLC3065
5/27
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