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STLC5048
January 2003
s
FULLY PROGRAMMABLE MONOLITHIC 4
CHANNEL CODEC/FILTER
s
SINGLE +3.3V SUPPLY
s
A/m LAW PROGRAMMABLE
s
LINEAR CODING (16 BITS) OPTION
s
PCM HIGHWAY FORMAT AUTOMATICALLY
DETECTED:1.536 or 1.544 MHz2.048, 4.096,
8192 MHz
s
TWO PCM PORTS AVAILABLE
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TX GAIN PROGRAMMING: 33dB RANGE;
<0.01dB STEP
s
RX GAIN PROGRAMMING:42dB RANGE;
<0.01dB STEP
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PROGRAMMABLE SLIC INPUT IMPEDANCE
s
PROGRAMMABLE TRANSHYBRID BALANCE
FILTER
s
PROGRAMMABLE EQUALIZATION
(FREQUENCY RESPONSE)
s
PROGRAMMABLE TIME SLOT ASSIGNMENT
s
DIGITAL AND ANALOG LOOPBACKS
s
SLIC CONTROL PORTSTATIC (16 I/Os)
DYNAMIC (12 I/Os + 4 CS)
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BUILT-IN TEST MODE WITH TONE
GENERATION, MCU ACCESS TO PCM DATA
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64 TQFP (10X10mm) PACKAGE
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PROGRAMMABLE SLIC LINE CURRENT
LIMITATION
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PROGRAMMABLE SLIC OFF-HOOK
DETECTION THRESHOLD
DESCRIPTION
The STLC5048 is a monolithic fully programmable 4
channel CODEC and filter. It operates with a single
+3.3V supply.
The analog interface is based on a receive output
buffer driving the SLIC RX input and on an amplifier
input stage normally driven by the SLIC TX output.
Due to the single supply voltage a midsupply refer-
ence level is generated internally by the device and
all analog signals are referred to this level (AGND).
The PCM interface uses one common 8KHz frame
sync. pulse for transmit and receive direction. The bit
clock is automatically detected between four stan-
dards: 1.563/1.544MHz, 2.048MHz, 4.096MHz,
8192MHz.
Two PCM port are provided: the channels can be
connected to port A or/and B.
Device programmability is achieved by means of
several registers and commands allowing to set the
different parameters like TX/RX gains, line imped-
ance, transhybrid balance, equalization (frequency
response), encoding law (A/
), time slot assignment,
independent channels power up/down, loopbacks,
PCM bits offset.
The STLC5048 can be programmed via serial inter-
face running up to 8 MHz. One interrupt output pin is
also provided.
A GUI interface is also available to emulate and pro-
gram the coefficients for impedance synthesis, echo
cancelling and channel filtering.
TQFP64 (10x10mm)
ORDERING NUMBER: STLC5048
FULLY PROGRAMMABLE
FOUR CHANNEL CODEC AND FILTER
STLC5048
2/45
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGE
THERMAL DATA
Symbol
Parameter
Value
Unit
V
CC
V
CC
to V
EE
4.6
V
V
DD
V
DD
to V
SS
4.6
V
VD
IN
Digital Input Pin Voltage
5.5
V
VAin
Analog Input Pin Voltage(V
DD
=V
CC
; V
EE
=V
SUB
)
V
CC
+ 0.5; V
EE
- 0.5
V
T
STG
Storage Temperature Range
-65 to +150
C
T
LEAD
Lead Temperature (soldering, 10s)
300
C
Symbol
Parameter
Value
Unit
V
CC
, V
DD
Supply Voltage
3.3 +/- 5%
V
T
OP
Operating Temperature Range
-40 to +85
C
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction-Ambient
70
C/W
D/A
CH0
PLL
BLOCK
ANALOG FRONT END
VCC
VEE
VDD
VSS
SUB
CAP
M1
M0
DIGITAL PROCESSOR
8
BIAS
GENER.
SLIC
THR
ITH
ILIM
VBG
D00TL467
DECODER
CONTROLLER
to analog FE
INTERPOLAT.
DECIMATORS
KD FILTERS
SLIC
INTERFACE
CONFIG.
REGISTERS
SERIAL
INTERFACE
SHAPPIRE
MACRO
CONTR
OL INTERF
A
C
E
COEFF B
U
S
DATA INTERFACE
A/U LAW
GR0
GX0
A/D
CH0
D/A
CH1
GR1
GX1
A/D
CH1
ENCODER
PCM
INTERFACE
FS
VFRO0
VFX10
VFRO1
VFX11
VFRO2
VFX12
VFRO3
VFX13
MCLK
DRA
DRB
DXA
DXB
TSXA
TSXB
IO11
IO10
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
CS3
CS2
CS1
CS0
INT
CCLK
CI
CO
CS
A/U LAW
D/A
CH2
GR2
GX2
A/D
CH2
D/A
CH3
GR3
GX3
A/D
CH3
8
16
16
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STLC5048
PIN CONNECTION (Top view)
PIN DESCRIPTION
I/O DEFINITION
Type
Definition
AI
Analog Input
AO
Analog Output
ODO
Open Drain Output
DI
Digital Input
DO
Digital Output
DIO
Digital Input / Output
DTO
Digital Tristate Output
DPS
Digital Power Supply
APS
Analog Power Supply
1
2
3
5
6
4
7
8
9
10
27
11
28 29 30 31 32
59 58 57 56
54
55
53 52 51 50 49
43
42
41
39
38
40
48
47
46
44
45
CI
CO
CS
N.C.
N.C.
INT
DXA
DRA
VDD
CCLK
VSS
IO3
IO4
IO5
VCC5
M0
VEE5
CS0_
CS1_
VEE1
VEE0
RES
IO9
IO10
IO11
VCC4
M1
VEE4
CS2_
CS3_
VEE2
VEE3
VBG
VFXI2
VFRO2
SUB
VFRO1
VFXI1
CAP
VFRO3
ILIM
VFXI3
VCC2
VCC3
D94TL150
22 23 24 25 26
60
IO8
61
IO7
62
IO6
63
N.C.
64
RES.
TSXB_
N.C.
IO0
IO1
IO2
17 18 19 20 21
37
36
34
33
35
VCC1
VCC0
ITH
VFRO0
VFXI0
12
13
14
15
16
DRB
DXB
FS
TSXA
MCLK
STLC5048
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PIN DESCRIPTION (continued)
ANALOG PIN DESCRIPTION
NOT CONNECTED
POWER SUPPLY PIN DESCRIPTION
No.
Name
Type
Description
33
VFRO0
AO
Receive analog amplifier output channel 0. PCM data received on
the programmed Time Slot on DR input is decoded and appears at
this output.
39
VFRO1
AO
Receive analog amplifier output channel 1. PCM data received on
the programmed Time Slot on DR input is decoded and appears at
this output.
42
VFRO2
AO
Receive analog amplifier output channel 2. PCM data received on
the programmed Time Slot on DR input is decoded and appears at
this output.
48
VFRO3
AO
Receive analog amplifier output channel 3. PCM data received on
the programmed Time Slot on DR input is decoded and appears at
this output.
35
VFXI0
AI
TX Input Amplifier channel 0. Typ 1M
input impedance
38
VFXI1
AI
TX Input Amplifier channel 1. Typ 1M
input impedance
43
VFXI2
AI
TX Input Amplifier channel 2. Typ 1M
input impedance
46
VFXI3
AI
TX Input Amplifier channel 3. Typ 1M
input impedance
40
CAP
AGND Voltage filter pin: a 100nF capacitor must be connected
between ground and this pin.
34
ITH
AO
SLIC Off Hook detection threshold.
47
ILIM
AO
SLIC line current limitation.
49
VBG
AI
SLIC VBG reference for DC characterisrics programmability.
2, 18, 63, 1
N.C.
Not Connected, must be left open
32, 64
RES
Reserved pins, must be connected to ground
25,36,
37,44,
45,56
VCC0..5
APS
Total 6 pins: 3.3V analog power supplies, should be shorted together,
require 100nF decoupling capacitor to VEE.
26,30,
31,50,
51,55
VEE0..5
APS
Total 6 pins: analog ground, should be shorted together.
9
VDD
DPS
Digital Power supply 3.3V, require 100nF decoupling capacitor to
VSS.
8
VSS
DPS
Digital Ground.
41
SUB
DPS
Substrate connection. Must be shorted together with VEE and VSS
pins.
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STLC5048
PIN DESCRIPTION (continued)
DIGITAL PIN DESCRIPTION
No.
Name
Type
Description
27
54
M0
M1
DI
Mode Select.
M1 M0 Mode select
0 0 Reset Status
1 0 Normal Operation
0 1 Not Allowed
1 1 Not Allowed
14
FS
DI
Frame Sync. Pulse. A pulse or a square waveform with an 8kHz
repetition rate is applied to this pin to define the start of the receive
and transmit frame. Effective start of the frame can be then shifted of
up to 7 clock pulses independently in receive and transmit directions
by proper programming of the PCMSH register.
13
MCLK
DI
Master Clock Input.
Four possible frequencies can be used:
1.536/1.544 MHz; 2.048 MHz; 4.096 MHz; 8.192 MHz.
The device automatically detect the frequency applied.
This signal is also used as bit clock and it is used to shift data into
and out of the DRA/B and DXA/B pins.
12
TSXA
ODO
Transmit Time Slot (open drain output, 3.2mA). Normally it is floating
in high impedance state except when a time slot is active on the DXA
output. In this case TSXA output pulls low to enable the backplane
line driver.
11
DXA
DTO
Transmit PCM interface A. It remains in high impedance state except
during the assigned time slots during which the PCM data byte is
shifted out on the rising edge of MCLK.
10
DRA
DI
Receive PCM interface A. It remains inactive except during the
assigned receive time slots during which the PCM data byte is shifted
in on the falling edge of MCLK.
24
IO5
DIO
General control I/O pin #5. Can be programmed as input or output via
DIR register. Depending on content of CONF register can be a static
input/output or a dynamic input/output synchronised with the CSn
output signals controlling the SLICs.
62
IO6
DIO
General control I/O pin #6. (see IO5 description).
61
IO7
DIO
General control I/O pin #7. (see IO5 description).
60
IO8
DIO
General control I/O pin #8. (see IO5 description).
59
IO9
DIO
General control I/O pin #9. (see IO5 description).
58
IO10
DIO
General control I/O pin #10. (see IO5 description).
57
IO11
DIO
General control I/O pin #11. (see IO5 description).
19
IO0
DIO
General control I/O pin #0. (see IO5 description).
20
IO1
DIO
General control I/O pin #1. (see IO5 description).
21
IO2
DIO
General control I/O pin #2. (see IO5 description).
22
IO3
DIO
General control I/O pin #3. (see IO5 description).
23
IO4
DIO
General control I/O pin #4. (see IO5 description).
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