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Электронный компонент: STP30NS15LFP

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1/9
July 2003
.
STP30NS15LFP
N-CHANNEL 150V - 0.085
- 10A TO-220FP
MESH OVERLAYTM POWER MOSFET
s
TYPICAL R
DS
(on) = 0.085
s
EXTREMELY HIGH dv/dt CAPABILITY
s
100% AVALANCHE TESTED
DESCRIPTION
Using the latest high voltage MESH OVERLAYTM
process, STMicroelectronics has designed an advanced
family of power MOSFETs with outstanding
performances. The new patent pending strip layout
coupled with the Company's proprietary edge termination
structure, gives the lowest RDS(on) per area,
exceptional avalanche and dv/dt capabilities and
unrivalled gate charge and switching characteristics.
APPLICATIONS
s
SWITCHING "S" CAPACITOR
TYPE
V
DSS
R
DS(on)
I
D
STP30NS15LFP
150 V
<0.1
10 A
1
2
3
TO-220FP
ABSOLUTE MAXIMUM RATINGS
(
)
Pulse width limited by safe operating area.
(1) Starting T
j
= 25
o
C, I
D
= 15A, V
DD
= 75V
(2) I
SD
35A, di/dt
300A/s, V
DD
V
(BR)DSS
, T
j
T
JMAX.
Symbol
Parameter
Value
Unit
V
DS
Drain-source Voltage (V
GS
= 0)
150
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
150
V
V
GS
Gate- source Voltage
15
V
I
D
Drain Current (continuous) at T
C
= 25C
10
A
I
D
Drain Current (continuous) at T
C
= 100C
7
A
I
DM
(
)
Drain Current (pulsed)
40
A
P
tot
Total Dissipation at T
C
= 25C
30
W
Derating Factor
0.2
W/C
E
AS
(1)
Single Pulse Avalanche Energy
300
mJ
dv/dt
(2)
Peak Diode Recovery voltage slope
2.4
V/ns
T
stg
Storage Temperature
-55 to 175
C
T
j
Operating Junction Temperature
INTERNAL SCHEMATIC DIAGRAM
STP30NS15LFP
2/9
THERMAL DATA
ELECTRICAL CHARACTERISTICS (T
case
= 25 C unless otherwise specified)
OFF
ON
(1)
DYNAMIC
Rthj-case
Rthj-amb
T
l
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Maximum Lead Temperature For Soldering Purpose
Max
Max
Typ
5
62.5
300
C/W
C/W
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source Breakdown
Voltage
I
D
= 250 A, V
GS
= 0
150
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
V
DS
= Max Rating T
C
= 125C
1
10
A
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= 15V
100
nA
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
I
D
= 250 A
1
2
3
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10 V
I
D
= 5 A
V
GS
= 5 V
I
D
= 5 A
0.085
0.1
0.1
0.112
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs (*)
Forward Transconductance
V
DS
= 20 V
I
D
= 7 A
6
S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0
1080
170
105
pF
pF
pF
3/9
STP30NS15LFP
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
(*)
Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
(
)
Pulse width limited by safe operating area.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(on)
t
r
Turn-on Delay Time
Rise Time
V
DD
= 75 V
I
D
= 5 A
R
G
= 4.7
V
GS
= 4.5 V
(Resistive Load, Figure 1)
25
95
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
=120V I
D
=10A V
GS
=5V
(see test circuit, Figure 2)
40
7.5
20
54
nC
nC
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(off)
t
f
Turn-off Delay Time
Fall Time
V
DD
= 75 V
I
D
= 5 A
R
G
= 4.7
,
V
GS
= 5 V
(Resistive Load, Figure 1)
55
30
ns
ns
t
r(Voff)
t
f
t
c
Off-voltage Rise Time
Fall Time
Cross-over Time
V
clamp
= 120 V
I
D
= 10 A
R
G
= 4.7
,
V
GS
= 4.5 V
(Inductive Load, Figure 3)
15
30
50
ns
ns
ns
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
I
SDM
(
)
Source-drain Current
Source-drain Current (pulsed)
10
40
A
A
V
SD
(*)
Forward On Voltage
I
SD
= 10 A
V
GS
= 0
1.3
V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 10 A
di/dt = 100A/s
V
r
= 30 V
T
j
= 150C
(Inductive Load, Figure 3)
160
950
12
ns
nC
A
ELECTRICAL CHARACTERISTICS (continued)
Safe Operating Area
Thermal Impedance
STP30NS15LFP
4/9
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
5/9
STP30NS15LFP
Normalized Gate Threshold Voltage vs Temperature
Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage vs Temperature
.
.
STP30NS15LFP
6/9
Fig. 2: Gate Charge test Circuit
Fig. 3: Test Circuit For Diode Recovery Behaviour
Fig. 1: Switching Times Test Circuits For Resistive
Load
7/9
STP30NS15LFP
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.4
4.6
0.173
0.181
B
2.5
2.7
0.098
0.106
D
2.5
2.75
0.098
0.108
E
0.45
0.7
0.017
0.027
F
0.75
1
0.030
0.039
F1
1.15
1.7
0.045
0.067
F2
1.15
1.7
0.045
0.067
G
4.95
5.2
0.195
0.204
G1
2.4
2.7
0.094
0.106
H
10
10.4
0.393
0.409
L2
16
0.630
L3
28.6
30.6
1.126
1.204
L4
9.8
10.6
0.385
0.417
L6
15.9
16.4
0.626
0.645
L7
9
9.3
0.354
0.366
3
3.2
0.118
0.126
L2
A
B
D
E
H
G
L6
F
L3
G1
1 2 3
F2
F1
L7
L4
TO-220FP MECHANICAL DATA
STP30NS15LFP
8/9
DIM.
mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 4.4
4.6
0.173
0.181
B 2.5
2.7
0.009
0.106
C 1
1.4
0.039
0.055
D 2.4
2.75
0.094
0.108
E 0.4
0.7
0.015
0.027
F 0.75
1 0.029
0.039
F1 1.15
1.7 0.045
0.066
F2 1.15
1.7 0.045
0.066
G 4.68
5.48
0.184
0.215
G1 2.24
2.84 0.088
0.111
H 10
10.4
0.393
0.409
L1 18.4
19.2 0.724
0.755
L2 16
0.629
L3 29
30 1.14
1.18
L4 15.3
16.1 0.60
0.63
L5 3.4
0.133
L6 15.9
16.4 0.625
0.665
L7 9
9.3
0.354
0.366
L8 22.5
23.6 0.885
0.929
M 4.6
5.4
0.181
0.212
N 2.29
3.29
0.090
0.129
Dia 3
3.2
TO-220FP(023Y) MECHANICAL DATA
9/9
STP30NS15LFP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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2003 STMicroelectronics - All Rights Reserved
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