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October 2003
STP40NF12
N-CHANNEL 120V - 0.028
- 40A TO-220
LOW GATE CHARGE STripFETTM II POWER MOSFET
(1) I
SD
40A, di/dt
600A/s, V
DD
V
(BR)DSS
, T
j
T
JMAX.
(2) Starting T
j
= 25C, I
D
= 40A, V
DD
= 50V
s
TYPICAL R
DS
(on) = 0.028
s
EXCEPTIONAL dv/dt CAPABILITY
s
100% AVALANCHE TESTED
s
APPLICATION ORIENTED
CHARACTERIZATION
DESCRIPTION
This Power MOSFET series realized with STMicro-
electronics unique STripFET process has specifical-
ly been designed to minimize input capacitance and
gate charge. It is therefore suitable as primary
switch in advanced high-efficiency isolated DC-DC
converters for Telecom and Computer application. It
is also intended for any application with low gate
charge drive requirements.
APPLICATIONS
s
HIGH-EFFICIENCY DC-DC CONVERTERS
s
UPS AND MOTOR CONTROL
ABSOLUTE MAXIMUM RATINGS
(
q
) Pulse width limited by safe operating area
TYPE
V
DSS
R
DS(on)
I
D
STP40NF12
120 V
< 0.032
40 A
Symbol
Parameter
Value
Unit
V
DS
Drain-source Voltage (V
GS
= 0)
120
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
120
V
V
GS
Gate- source Voltage
20
V
I
D
Drain Current (continuous) at T
C
= 25C
40
A
I
D
Drain Current (continuous) at T
C
= 100C
28
A
I
DM
( )
Drain Current (pulsed)
160
A
P
TOT
Total Dissipation at T
C
= 25C
150
W
Derating Factor
1
W/C
dv/dt (1)
Peak Diode Recovery voltage slope
14
V/ns
E
AS
(2)
Single Pulse Avalanche Energy
150
mJ
T
stg
Storage Temperature
55 to 175
C
T
j
Operating Junction Temperature
TO-220
1
2
3
INTERNAL SCHEMATIC DIAGRAM
STP40NF12
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THERMAL DATA
ELECTRICAL CHARACTERISTICS (T
CASE
= 25 C UNLESS OTHERWISE SPECIFIED)
OFF
ON (1)
DYNAMIC
Rthj-case
Thermal Resistance Junction-case Max
1
C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
62.5
C/W
T
l
Maximum Lead Temperature For Soldering Purpose
300
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 250 A, V
GS
= 0
120
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
1
A
V
DS
= Max Rating, T
C
= 125 C
10
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= 20V
100
nA
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250A
2
2.8
4
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, I
D
= 20 A
0.028
0.032
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs
(1)
Forward Transconductance
V
DS
= 25V
,
I
D
= 20 A
40
S
C
iss
Input Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0
1880
pF
C
oss
Output Capacitance
265
pF
C
rss
Reverse Transfer
Capacitance
110
pF
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STP40NF12
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(on)
Turn-on Delay Time
V
DD
= 50 V, I
D
= 20 A
R
G
= 4.7
V
GS
= 10V
(see test circuit, Figure 3)
28
ns
t
r
Rise Time
63
ns
Q
g
Total Gate Charge
V
DD
= 80V, I
D
=40A,V
GS
= 10V
60
80
nC
Q
gs
Gate-Source Charge
11
nC
Q
gd
Gate-Drain Charge
21
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(off)
t
f
Turn-off-Delay Time
Fall Time
V
DD
= 50 V, I
D
= 20 A,
R
G
= 4.7
,
V
GS
= 10V
(see test circuit, Figure 3)
84
28
ns
ns
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
Source-drain Current
40
A
I
SDM
(2)
Source-drain Current (pulsed)
160
A
V
SD
(1)
Forward On Voltage
I
SD
= 40 A, V
GS
= 0
1.3
V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 40 A, di/dt = 100A/s,
V
DD
= 25V, T
j
= 150C
(see test circuit, Figure 5)
114
456
8
ns
nC
A
Thermal Impedance
Safe Operating Area
STP40NF12
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Transconductance
Static Drain-source On Resistance
Output Characteristics
Transfer Characteristics
Gate Charge vs Gate-source Voltage
Capacitance Variations
5/8
STP40NF12
Normalized Gate Threshold Voltage vs
Temperature
Source-drain Diode Forward Characteristics
Normalized On Resistance vs Temperature
Normalized Drain-Source Breakdown vs
Temperature
STP40NF12
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Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
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STP40NF12
DIM.
mm.
inch
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
4.40
4.60
0.173
0.181
b
0.61
0.88
0.024
0.034
b1
1.15
1.70
0.045
0.066
c
0.49
0.70
0.019
0.027
D
15.25
15.75
0.60
0.620
E
10
10.40
0.393
0.409
e
2.40
2.70
0.094
0.106
e1
4.95
5.15
0.194
0.202
F
1.23
1.32
0.048
0.052
H1
6.20
6.60
0.244
0.256
J1
2.40
2.72
0.094
0.107
L
13
14
0.511
0.551
L1
3.50
3.93
0.137
0.154
L20
16.40
0.645
L30
28.90
1.137
P
3.75
3.85
0.147
0.151
Q
2.65
2.95
0.104
0.116
TO-220 MECHANICAL DATA
STP40NF12
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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2003 STMicroelectronics - Printed in Italy - All Rights Reserved
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