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April 2004
STP6NK50Z - STF6NK50Z
STD6NK50Z
N-CHANNEL 500V - 0.93
- 5.6A TO-220/TO-220FP/DPAK
Zener-Protected SuperMESHTM MOSFET
s
TYPICAL R
DS
(on) = 0.93
s
EXTREMELY HIGH dv/dt CAPABILITY
s
100% AVALANCHE TESTED
s
GATE CHARGE MINIMIZED
s
VERY LOW INTRINSIC CAPACITANCES
s
VERY GOOD MANUFACTURING
REPEATIBILITY
DESCRIPTION
The SuperMESHTM series is obtained through an
extreme optimization of ST's well established strip-
based PowerMESHTM layout. In addition to pushing
on-resistance significantly down, special care is tak-
en to ensure a very good dv/dt capability for the
most demanding applications. Such series comple-
ments ST full range of high voltage MOSFETs in-
cluding revolutionary MDmeshTM products.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
IDEAL FOR OFF-LINE POWER SUPPLIES,
ADAPTORS AND PFC
s
LIGHTING
ORDER CODES
TYPE
V
DSS
R
DS(on)
I
D
Pw
STP6NK50Z
STF6NK50Z
STD6NK50Z
500 V
500 V
500 V
< 1.2
< 1.2
< 1.2
5.6 A
5.6 A
5.6 A
90 W
25 W
90 W
PART NUMBER
MARKING
PACKAGE
PACKAGING
STP6NK50Z
P6NK50Z
TO-220
TUBE
STF6NK50Z
F6NK50Z
TO-220FP
TUBE
STD6NK50ZT4
D6NK50Z
DPAK
TAPE & REEL
TO-220
TO-220FP
1
2
3
1
3
DPAK
INTERNAL SCHEMATIC DIAGRAM
STP6NK50Z - STF6NK50Z - STD6NK50Z
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ABSOLUTE MAXIMUM RATINGS
( ) Pulse width limited by safe operating area
(1) I
SD
5.6A, di/dt
200 A/s, V
DD
V
(BR)DSS
, T
j
T
JMAX.
(*) Limited only by maximum temperature allowed
THERMAL DATA
AVALANCHE CHARACTERISTICS
GATE-SOURCE ZENER DIODE
PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the
usage of external components.
Symbol
Parameter
Value
Unit
STP6NK50Z
STD6NK50Z
STF6NK50Z
V
DS
Drain-source Voltage (V
GS
= 0)
500
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
500
V
V
GS
Gate- source Voltage
30
V
I
D
Drain Current (continuous) at T
C
= 25C
5.6
5.6 (*)
A
I
D
Drain Current (continuous) at T
C
= 100C
3.5
3.5 (*)
A
I
DM
( )
Drain Current (pulsed)
22.4
22.4 (*)
A
P
TOT
Total Dissipation at T
C
= 25C
90
25
W
Derating Factor
0.72
0.2
W/C
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=1.5K
)
3000
V
dv/dt (1)
Peak Diode Recovery voltage slope
4.5
V/ns
V
ISO
Insulation Withstand Voltage (DC)
-
2500
V
T
j
T
stg
Operating Junction Temperature
Storage Temperature
-55 to 150
C
TO-220
DPAK
TO-220FP
Rthj-case
Thermal Resistance Junction-case Max
1.38
5
C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
62.5
C/W
T
l
Maximum Lead Temperature For Soldering Purpose
300
C
Symbol
Parameter
Max Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
5.6
A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 C, I
D
= I
AR
, V
DD
= 50 V)
180
mJ
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
BV
GSO
Gate-Source Breakdown
Voltage
Igs= 1mA (Open Drain)
30
V
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STP6NK50Z - STF6NK50Z - STD6NK50Z
ELECTRICAL CHARACTERISTICS (T
CASE
=25C UNLESS OTHERWISE SPECIFIED)
ON/OFF
DYNAMIC
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
3. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80%
V
DSS
.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 1 mA, V
GS
= 0
500
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
V
DS
= Max Rating, T
C
= 125 C
1
50
A
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= 20V
10
A
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 50A
3
3.75
4.5
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, I
D
= 2.8 A
0.93
1.2
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs
(1)
Forward Transconductance
V
DS
= 8 V
,
I
D
= 2.8 A
4.3
S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0
690
100
20
pF
pF
pF
C
oss eq.
(3)
Equivalent Output
Capacitance
V
GS
= 0V, V
DS
= 0V to 400V
52
pF
t
d(on)
t
r
t
d(off)
t
f
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
V
DD
= 250 V, I
D
= 2.8 A
R
G
= 4.7
V
GS
= 10 V
(Resistive Load see, Figure 3)
12
23.5
31
23
ns
ns
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 400V, I
D
= 5.6 A,
V
GS
= 10V
24.6
4.9
13.3
nC
nC
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
I
SDM
(2)
Source-drain Current
Source-drain Current (pulsed)
5.6
22.4
A
A
V
SD
(1)
Forward On Voltage
I
SD
= 5.6 A, V
GS
= 0
1.6
V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 5.6 A, di/dt = 100 A/s
V
DD
= 48V, T
j
= 25C
(see test circuit, Figure 5)
254
1.2
10
ns
C
A
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 5.6 A, di/dt = 100 A/s
V
DD
= 48V, T
j
= 150C
(see test circuit, Figure 5)
360
1.9
11
ns
C
A
STP6NK50Z - STF6NK50Z - STD6NK50Z
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Thermal Impedance for DPAK
Safe Operating Area for DPAK
Thermal Impedance for TO-220FP
Safe Operating Area for TO-220FP
Thermal Impedance for TO-220
Safe Operating Area for TO-220
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STP6NK50Z - STF6NK50Z - STD6NK50Z
Transconductance
Transfer Characteristics
Output Characteristics
Capacitance Variations
Gate Charge vs Gate-source Voltage
Static Drain-source On Resistance
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