STP7NB80
STP7NB80FP
N - CHANNEL 800V - 1.2
- 6.5A - TO-220/TO-220FP
PowerMESH
TM
MOSFET
s
TYPICAL R
DS(on)
= 1.2
s
EXTREMELY HIGH dv/dt CAPABILITY
s
100% AVALANCHE TESTED
s
VERY LOW INTRINSIC CAPACITANCES
s
GATE CHARGE MINIMIZED
DESCRIPTION
Using the latest high voltage MESH OVERLAY
TM
process, STMicroelectronics has designed an
advanced family
of
power MOSFETs
with
outstanding performances.
The
new
patent
pending strip layout coupled with the Company's
proprietary edge termination structure, gives the
lowest RDS(on) per area, exceptional avalanche
and dv/dt capabilities and unrivalled gate charge
and switching characteristics.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
SWITCH MODE POWER SUPPLIES (SMPS)
s
DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
INTERNAL SCHEMATIC DIAGRAM
April 1999
TO-220
TO-220FP
1
2
3
1
2
3
TYPE
V
DSS
R
DS(on)
I
D
ST P7NB80
ST P7NB80FP
800 V
800 V
< 1.5
< 1.5
6.5 A
6.5 A
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Un it
STP7NB80
STP7NB80F P
V
DS
Drain-source Volt age (V
GS
= 0)
800
V
V
DGR
Drain- gate Voltage (R
GS
= 20 k
)
800
V
V
GS
Gate-source Voltage
30
V
I
D
Drain Current (continuous) at T
c
= 25
o
C
6.5
6.5(*)
A
I
D
Drain Current (continuous) at T
c
= 100
o
C
4.1
4.1(*)
A
I
DM
(
)
Drain Current (pulsed)
26
26
A
P
tot
T otal Dissipation at T
c
= 25
o
C
135
40
W
Derat ing Factor
1.08
0.32
W /
o
C
dv/dt (
1
)
Peak Diode Recovery voltage slope
4.5
4.5
V/ns
V
ISO
Insulat ion Withstand Voltage (DC)
--
2000
o
C
T
s tg
Storage Temperat ure
-65 to 150
o
C
T
j
Max. Operat ing Junction T emperature
150
o
C
(
) Pulse width limited by safe operating area
(
1
) I
SD
6.5A, di/dt
200 A/
s, V
DD
V
( BR)DSS
, Tj
T
JMAX
(
*) Limited only maximum temperature allowed
1/9
THERMAL DATA
TO-220
TO-220FP
R
thj -case
Thermal Resistance Junction-case
Max
0.92
3.13
o
C/W
R
thj -amb
R
thc-sink
T
l
Thermal Resistance Junction-ambient
Max
Thermal Resistance Case-sink
Typ
Maximum Lead Temperature For Soldering Purpose
62.5
0.5
300
o
C/W
o
C/W
o
C
AVALANCHE CHARACTERISTICS
Symbo l
Parameter
Max Valu e
Unit
I
AR
Avalanche Current , Repet itive or Not-Repet itive
(pulse width limited by T
j
max)
6. 5
A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25
o
C, I
D
= I
AR
, V
DD
= 50 V)
400
mJ
ELECTRICAL CHARACTERISTICS (T
case
= 25
o
C unless otherwise specified)
OFF
Symbo l
Parameter
Test Con ditions
Min.
T yp.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 250
A
V
GS
= 0
800
V
I
DSS
Zero G ate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
V
DS
= Max Rating
T
c
= 125
o
C
1
50
A
A
I
G SS
Gat e-body Leakage
Current (V
DS
= 0)
V
GS
=
30 V
100
nA
ON (
)
Symbo l
Parameter
Test Con ditions
Min.
T yp.
Max.
Unit
V
G S(th)
Gat e Threshold
Voltage
V
DS
= V
GS
I
D
= 250
A
3
4
5
V
R
DS(on)
Static Drain-source O n
Resist ance
V
GS
= 10V
I
D
= 3.2 A
1.2
1. 5
I
D(o n)
On Stat e Drain Current
V
DS
> I
D(o n)
x R
DS(on )ma x
V
GS
= 10 V
6. 5
A
DYNAMIC
Symbo l
Parameter
Test Con ditions
Min.
T yp.
Max.
Unit
g
f s
(
)
Forward
Transconduct ance
V
DS
> I
D(o n)
x R
DS(on )ma x
I
D
= 3.2 A
1. 5
6.5
S
C
iss
C
os s
C
rss
Input Capacitance
Out put Capacitance
Reverse T ransfer
Capacitance
V
DS
= 25 V
f = 1 MHz
V
GS
= 0
1400
180
20
pF
pF
pF
STP7NB80/FP
2/9
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
Parameter
Test Con ditions
Min.
T yp.
Max.
Unit
t
d(on)
t
r
Turn-on Time
Rise Time
V
DD
= 400 V
I
D
= 3.5 A
R
G
= 4.7
V
G S
= 10 V
(see test circuit, figure 3)
20
10
ns
ns
Q
g
Q
gs
Q
gd
Tot al Gate Charge
Gat e-Source Charge
Gat e-Drain Charge
V
DD
= 640 V
I
D
= 7 A V
GS
= 10 V
R
G
= 4.7
40
10
18
52
nC
nC
nC
SWITCHING OFF
Symbo l
Parameter
Test Con ditions
Min.
T yp.
Max.
Unit
t
r (Voff)
t
f
t
c
Off -volt age Rise Time
Fall Time
Cross-over Time
V
DD
= 640 V
I
D
= 7 A
R
G
= 4.7
V
GS
= 10 V
(see test circuit, figure 5)
15
15
25
ns
ns
ns
SOURCE DRAIN DIODE
Symbo l
Parameter
Test Con ditions
Min.
T yp.
Max.
Unit
I
SD
I
SDM
(
)
Source-drain Current
Source-drain Current
(pulsed)
6. 5
26
A
A
V
SD
(
)
Forward On Volt age
I
SD
= 6. 5 A
V
GS
= 0
1. 6
V
t
rr
Q
rr
I
RRM
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I
SD
= 7 A
di/dt = 100 A/
s
V
DD
= 100 V
T
j
= 150
o
C
(see test circuit, figure 5)
750
7.10
19
ns
C
A
(
) Pulsed: Pulse duration = 300
s, duty cycle 1.5 %
(
) Pulse width limited by safe operating area
Safe Operating Area for TO-220
Safe Operating Area for TO-220FP
STP7NB80/FP
3/9
Thermal Impedance for TO-220
Output Characteristics
Transconductance
Thermal Impedance for TO-220FP
Transfer Characteristics
Static Drain-source On Resistance
STP7NB80/FP
4/9
Gate Charge vs Gate-source Voltage
Normalized Gate Threshold Voltage vs
Temperature
Source-drain Diode Forward Characteristics
Capacitance Variations
Normalized On Resistance vs Temperature
STP7NB80/FP
5/9
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 2: Unclamped Inductive Waveform
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
STP7NB80/FP
6/9
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.40
4.60
0.173
0.181
C
1.23
1.32
0.048
0.051
D
2.40
2.72
0.094
0.107
D1
1.27
0.050
E
0.49
0.70
0.019
0.027
F
0.61
0.88
0.024
0.034
F1
1.14
1.70
0.044
0.067
F2
1.14
1.70
0.044
0.067
G
4.95
5.15
0.194
0.203
G1
2.4
2.7
0.094
0.106
H2
10.0
10.40
0.393
0.409
L2
16.4
0.645
L4
13.0
14.0
0.511
0.551
L5
2.65
2.95
0.104
0.116
L6
15.25
15.75
0.600
0.620
L7
6.2
6.6
0.244
0.260
L9
3.5
3.93
0.137
0.154
DIA.
3.75
3.85
0.147
0.151
L6
A
C
D
E
D1
F
G
L7
L2
Dia.
F1
L5
L4
H2
L9
F2
G1
TO-220 MECHANICAL DATA
P011C
STP7NB80/FP
7/9
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.4
4.6
0.173
0.181
B
2.5
2.7
0.098
0.106
D
2.5
2.75
0.098
0.108
E
0.45
0.7
0.017
0.027
F
0.75
1
0.030
0.039
F1
1.15
1.7
0.045
0.067
F2
1.15
1.7
0.045
0.067
G
4.95
5.2
0.195
0.204
G1
2.4
2.7
0.094
0.106
H
10
10.4
0.393
0.409
L2
16
0.630
L3
28.6
30.6
1.126
1.204
L4
9.8
10.6
0.385
0.417
L6
15.9
16.4
0.626
0.645
L7
9
9.3
0.354
0.366
3
3.2
0.118
0.126
L2
A
B
D
E
H
G
L6
F
L3
G1
1 2 3
F2
F1
L7
L4
TO-220FP MECHANICAL DATA
STP7NB80/FP
8/9
Information furnished is believ ed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are
subjec t to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
1999 STMicroelectronics Printed in Italy All Rights Reserved
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9/9
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