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July 2003
s
4-CHANNEL SERIAL-IN PARALLEL-IN LOW
SIDE PRE-FET DRIVER
s
DEVICES ARE CASCADABLE
s
INTERNAL 55V INDUCTIVE LOAD CLAMP
AND VGS PROTECTION CLAMP FOR
EXTERNAL POWER FETS
s
INDEPENDENT SHORTED-LOAD AND
SHORT-TO-BATTERY FAULT DETECTION
ON ALL GATE TERMINALS
s
INDEPENDENT OFF-STATE OPEN-LOAD
FAULT SENSE
s
OVER-BATTERY-VOLTAGE LOCKOUT
PROTECTION AND FAULT REPORTING
s
UNDER-BATTERY VOLTAGE LOCKOUT
PROTECTION
s
ASYNCRONOUS OPEN-GATE FAULT FLAG
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DEVICE OUTPUT CAN BE WIRED OR WITH
MULTIPLE DEVICES
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FAULT STATUS RETURNED THROUGH
SERIAL OUTPUT TERMINAL
s
INTERNAL GLOBAL POWER-ON RESET OF
DEVICE AND EXTERNAL RESET TERMINAL
s
HIGH IMPEDANCE CMOS COMPATIBLE
INPUTS WITH HYSTERESIS
s
TRANSITION FROM THE GATE OUTPUT TO
A LOW DUTY CYCLE PWM MODE WHEN A
SHORTED LOAD FAULT OCCURS
DESCRIPTION
The STPIC44L02 is a low-side predriver that
provides serial and parallel input interfaces to
control four external FET power switches.
It is mainly designed to provide low-frequency
switching, inductive load applications such as
solenoids and relays. Fault status is available in a
serial-data format. Each driver channel has
independent off-state open-load detection and
on-state shorted load short to battery detection.
The STPIC44L02 offers a battery over voltage and
undervoltage detection and shutdown. If a fault
occurs while using the STPIC44L02, the channel
transitates into a low duty cycle, pulse width
modulated (PWM) signal as long as the fault is
present.
These devices provide control of output channels
through a serial input interface or a parallel input
interface. A command to enable the output from
either interface enables the respective channels
gate output to the external FET. The serial
interface is recommended when the number of
signals between the control device and the
predriver
are
minimized
and
the
speed
of
operation is not critical. In applications where the
predriver
must
respond
very
quickly
or
asynchronously, the parallel input interface is
recommended.
For serial operation, the control device must
transitate CS from high to low to activate the serial
input interface. When this occurs, SDO, is
enabled, fault data is latched into the serial
interface, and the fault flag is refreshed. Data is
clocked into the serial registers on low to high
transitions of SCLK through SDI. Each string of
data must consist of at least four bits of data. In
applications where multiple devices are cascaded
together, the string of data must consist of four bits
for each device. A high data bit turns the
respective output channel on and a low data bit
turns it off. Fault data for the device is clocked out
of SDO as serial input data is clocked into the
device. Fault data consists of fault flags for
shorted load and open load flags (bits 0-3) for
each of the four output channels. Fault register
bits are set or cleared asynchronously to reflect
the current state of the hardware. A fault must be
present when CS is transitated from high to low to
be captured and reported in the serial fault data.
New faults cannot be captured in the serial
register when CS is low. CS must be transitated
high after all of the serial data has been clocked
into the device. A low to high transition of CS
transfers the last four bits of serial data to the
STPIC44L02
4 CHANNEL SERIAL AND PARALLEL
LOW SIDE PRE-FET DRIVER
SOP
STPIC44L02
2/21
output buffer that puts SDO in a high impedance
state and clears and reenables the fault register.
The STPIC44L02 was designed to allow the serial
input interfaces of multiple devices to be cascated
together to simplify the serial interface of the
controller. Serial input data flows through the
device and is transferred out SDO following the
fault data in cascaded configurations.
For parallel operation, data is transferred directly
from the parallel input interface IN0-IN3 to the
respective GATE(0-3) output asynchronously.
SCLK or CS is not required for parallel control. A 1
on the parallel input turns the respective channel
on, where as a 0 turns it off. Note that either the
serial input interface or the parallel input interface
can enable a channel. Under parallel operation,
fault data must still be collected through the serial
data interface.
The predriver monitors the drain voltage for each
channel to detect shorted load or open load fault
conditions, in the on and off state respectively.
These devices offer the option of using an
internally generated fault reference voltage or an
externally supplied fault reference voltage through
V
COMP
for fault detection. The internal fault
reference is selected by connecting V
COMPEN
to
GND and the external reference is selected by
connecting V
COMPEN
to V
CC
. The drain voltage is
compared to the fault reference when the channel
is turned on to detect shorted load conditions and
when the channel is off to detect open load
conditions.
If
a
fault
occurs,
the
channel
transitates into a low duty cycle, pulse width
modulated (PWM) signal as long as the fault is
present. Shorted load fault conditions must be
present for at least the shorted load deglicth time,
t
(STBDG)
, to be flagged as a fault. A fault flag is
sent to the control device as well as the serial fault
register bits. More detail on fault detection
operation is presented in the device operation
section of this datasheet.
The device provides protection from over battery
voltage and under battery voltage conditions
irrespective of the state of the output channels.
When the battery voltage is greater than the
overvoltage
threshold
or
less
than
the
undervotlage threshold, all channels are disabled
and a fault flag is generated. Battery voltage faults
are not reported in the serial fault data. The
outputs return to normal operation once the
battery voltage fault has been corrected. When an
over
battery/under
battery
voltage
condition
occurs, the device reports the battery fault, but
disables fault reporting for open and shorted load
conditions. Fault reporting for open and shorted
load conditions are reenabled after the battery
fault condition has been corrected.
This device provides inductive transient protection
on all channels. The drain voltage is clamped to
protect the FET. The clamp voltage is defined by
the sum of V
CC
and turn on voltage of the external
FET. The predriver also provides a gate to source
voltage (V
GS
) clamp to protect the gate source
terminals of the power FET from exceeding their
rated voltages. An external active low RESET is
provided to clear all register and flags in the
device. GATE(0-3) outputs are disabled after
RESET has been pulled low.
The device provide pull-down resistors on all
inputs except CS and RESET. A pull-up resistor is
used on CS and RESET.
ORDERING CODES
Type
Package
Comments
STPIC44L02PTR
SSOP24 (Tape & Reel)
1350 parts per reel
STPIC44L02
3/21
Figure 1 : Schematic Diagram
STPIC44L02
4/21
PIN DESCRIPTION
PIN No
SYMBOL
I/O
NAME AND FUNCTION
1
FLT
I
Fault Flag. FLT is a logic level open-drain output that provides a real time fault flag for
shorted-load, open-load, over-battery voltage, under-battery voltage faults. The
device can be ORed with FLT terminals on other devices for interrupt handling. FLT
requires an external pull-up resistor.
2
VCOMPEN
I
Fault reference voltage select. VCOMPEN selects the internally generated fault
reference voltage (0) or an external fault reference (1) to be used in the shorted and
open load fault detection circuitry.
3
VCOMP
I
Fault reference voltage. VCOMP provides an external fault reference voltage for the
shorted-load and open load fault detection circuitry.
4
5
6
7
IN0
IN1
IN2
IN3
I
Parallel gate driver. IN0 trough In3 are real-time controls for the gate pre drive
circuitry. They are CMOS compatible with hysteresis.
8
CS
I
Chip select. A high to low transition on CS enables SDO, latches fault data into the
serial interface, and refreshes FLT. When CS is high, the fault register can change
fault status. On the falling edge of CS, fault data is latched into the serial output
register and transferred using SDO and SCLK. On a low to high transition of CS,
serial data is latched in to the output control register.
9
SDO
O
Serial data output. SDO is a 3-state output that transfers fault data to the controlling
device. It also passes serial input data to the next stage for cascaded operation. SDO
is taken to a high-impedance state when CS is in a high state.
10
SDI
I
Serial data input. Output control data is clocked into the serial register through SDI. A
1 on SDI commands a particular gate output on and a 0 turns it off.
11
SCLK
I
Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial
fault data is clocked out of SDO on the falling edge of the serial clock.
12
V
CC
I
Logic Supply Voltage
13
GND
I
Ground
14
16
19
21
DRAIN0
DRAIN1
DRAIN2
DRAIN3
I
FET drain inputs. DRAIN0 through DRAIN3 are used for both open load and short
circuit fault detection at the drain of the external FETs. They are also used for
inductive transient protection.
15
17
18
20
GATE0
GATE1
GATE2
GATE3
O
Gate drive output. GATE0 through GATE3 outputs are derived from the V
BAT
supply
voltage. Internal clamps prevent voltages on these nodes from exceeding the VGS
rating of most FETs.
22
RESET
I
Reset. A high-to low transition of RESET clears all registers and flags. Gate outputs
turn off and the FLT flag is cleared.
23
NC
Not Connected
24
V
BAT
I
Battery Supply Voltage
STPIC44L02
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Figure 2 : Pin Configuration
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
Note 1: All voltage value are with respect to GND
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
CC
Logic Supply Voltage (See Note 1)
-0.3 to 7
V
V
BAT
Battery Supply Voltage
-0.3 to 60
V
V
I
Logic Input Voltage Range
-0.3 to 7
V
V
O
Output Voltage (SDO and FLT)
-0.3 to 7
V
V
O
Output Voltage
-0.3 to 15
V
V
I
Logic Input Voltage Range
-0.3 to 7
V
V
DS
Drain to Source Voltage
-0.3 to 60
V
T
C
Operating Case Temperature Range
-40 to +125
C
T
J
Maximum Junction Temperature
150
C
T
stg
Storage Temperature Range
-40 to +150
C
Symbol
Parameter
Min.
Min.
Max.
Unit
V
CC
Logic Supply Voltage
4.5
5
5.5
V
V
BAT
Battery Supply Voltage
8
24
V
V
IH
High Level Input Voltage
0.85V
CC
V
CC
V
V
IL
Low Level Input Voltage
0
0.15V
CC
V
t
s
Set-up Time, SDI High Before SCLK
10
ns
t
h
Hold Time, SDI High After SCLK
10
ns
T
C
Operating Case Temperature
-40
125
C
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