STW50N10
N - CHANNEL ENHANCEMENT MODE
POWER MOS TRANSISTOR
s
TYPICAL R
DS(on)
= 0.027
s
AVALANCHE RUGGED TECHNOLOGY
s
100% AVALANCHE TESTED
s
REPETITIVE AVALANCHE DATA AT 100
o
C
s
HIGH CURRENT CAPABILITY
s
175
o
C OPERATING TEMPERATURE
s
APPLICATION ORIENTED
CHARACTERIZATION
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
POWER MOTOR CONTROL
s
DC-DC & DC-AC CONVERTERS
s
SYNCRONOUS RECTIFICATION
INTERNAL SCHEMATIC DIAGRAM
January 1998
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Val ue
Uni t
V
DS
Drain-source Voltage (V
GS
= 0)
100
V
V
DGR
Drain- gate Voltage (R
G S
= 20 k
)
100
V
V
GS
Gate-source Voltage
20
V
I
D
Drain Current (cont inuous) at T
c
= 25
o
C
50
A
I
D
Drain Current (cont inuous) at T
c
= 100
o
C
35
A
I
DM
(
)
Drain Current (pulsed)
200
A
P
t ot
Tot al Dissipation at T
c
= 25
o
C
180
W
Derating Fact or
1.2
W/
o
C
T
stg
St orage Temperature
-65 to 175
o
C
T
j
Max. Operat ing Junction Temperat ure
175
o
C
(
) Pulse width limited by safe operating area
I
SD
60 A, di/dt
200 A/
s, V
DD
V
(BR)DSS
, T
j
T
JMAX
TYPE
V
DSS
R
DS(on)
I
D
ST W50N10
100 V
< 0.035
50 A
TO-247
1
2
3
1/8
THERMAL DATA
R
t hj-ca se
R
t hj- amb
R
thc- si nk
T
l
Thermal Resistance Junction-case
Max
Thermal Resistance Junction-ambient
Max
Thermal Resistance Case-sink
T yp
Maximum Lead Temperature For Soldering Purpose
0.83
30
0.1
300
o
C/W
o
C/W
o
C/W
o
C
AVALANCHE CHARACTERISTICS
Symb ol
Parameter
Max Valu e
Uni t
I
AR
Avalanche Current, Repetitive or Not -Repet itive
(pulse width limited by T
j
max,
< 1%)
50
A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25
o
C, I
D
= I
AR
, V
DD
= 25 V)
400
mJ
ELECTRICAL CHARACTERISTICS (T
case
= 25
o
C unless otherwise specified)
OFF
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
V
(BR)DSS
Drain-source
Breakdown Volt age
I
D
= 250
A
V
GS
= 0
100
V
I
DSS
Zero G ate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
V
DS
= Max Rating
T
c
= 125
o
C
1
10
A
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
G S
=
20 V
100
nA
ON (
)
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
V
GS(th)
Gate Threshold
Voltage
V
DS
= V
GS
I
D
= 250
A
2
3
4
V
R
DS( on)
St atic Drain-source On
Resistance
V
G S
= 10 V
I
D
= 25 A
0.027
0.035
I
D(o n)
On St ate Drain Current
V
DS
> I
D(on)
x R
DS(on) max
V
G S
= 10 V
50
A
DYNAMIC
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
g
fs
(
)
Forward
Transconduct ance
V
DS
> I
D(on)
x R
DS(on) max
I
D
= 25 A
20
45
S
C
iss
C
oss
C
rss
Input Capacitance
Output Capacit ance
Reverse T ransfer
Capacitance
V
DS
= 25 V
f = 1 MHz
V
GS
= 0
4100
600
150
5200
800
200
pF
pF
pF
STW50N10
2/8
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
t
d(on)
t
r
Turn-on Time
Rise Time
V
DD
= 50 V
I
D
= 25 A
R
G
= 4.7
V
G S
= 10 V
25
75
35
105
ns
ns
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DD
= 80 V
I
D
= 50 A
V
GS
= 10 V
120
20
50
170
nC
nC
nC
SWITCHING OFF
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
t
r(Vof f)
t
f
t
c
Of f-voltage Rise Time
Fall Time
Cross-over Time
V
DD
= 80 V
I
D
= 50 A
R
G
= 4.7
V
GS
= 10 V
30
35
65
45
50
95
ns
ns
ns
SOURCE DRAIN DIODE
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
I
SD
I
SDM
(
)
Source-drain Current
Source-drain Current
(pulsed)
50
200
A
A
V
SD
(
)
Forward On Voltage
I
SD
= 50 A
V
GS
= 0
1.5
V
t
rr
Q
rr
I
RRM
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I
SD
= 50 A
di/ dt = 100 A/
s
V
DD
= 30 V
T
j
= 150
o
C
200
1.4
14
ns
C
A
(
) Pulsed: Pulse duration = 300
s, duty cycle 1.5 %
(
) Pulse width limited by safe operating area
(
1
) I
SD
60 A, di/dt
200 A/
s, V
DD
V
(BR)DSS
, T
j
T
JMAX
Safe Operating Area
Thermal Impedance
STW50N10
3/8
Output Characteristics
Transconductance
Gate Charge vs Gate-source Voltage
Transfer Characteristics
Static Drain-source On Resistance
Capacitance Variations
STW50N10
4/8
Normalized Gate Threshold Voltage vs
Temperature
Source-drain Diode Forward Characteristics
Normalized On Resistance vs Temperature
STW50N10
5/8
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 2: Unclamped Inductive Waveform
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
STW50N10
6/8
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.7
5.3
0.185
0.209
D
2.2
2.6
0.087
0.102
E
0.4
0.8
0.016
0.031
F
1
1.4
0.039
0.055
F3
2
2.4
0.079
0.094
F4
3
3.4
0.118
0.134
G
10.9
0.429
H
15.3
15.9
0.602
0.626
L
19.7
20.3
0.776
0.779
L3
14.2
14.8
0.559
0.413
0.582
L4
34.6
1.362
L5
5.5
0.217
M
2
3
0.079
0.118
Dia
3.55
3.65
0.140
0.144
P025P
TO-247 MECHANICAL DATA
STW50N10
7/8
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
1998 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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STW50N10
8/8
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