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August 2002
STY60NM50
N-CHANNEL 500V - 0.045
- 60A Max247
Zener-Protected MDmeshTMPower MOSFET
n
TYPICAL R
DS
(on) = 0.045
n
HIGH dv/dt AND AVALANCHE CAPABILITIES
n
IMPROVED ESD CAPABILITY
n
LOW INPUT CAPACITANCE AND GATE
CHARGE
n
LOW GATE INPUT RESISTANCE
n
TIGHT PROCESS CONTROL
n
INDUSTRY'S LOWEST ON-RESISTANCE
DESCRIPTION
The MDmeshTM
is a new revolutionary MOSFET
technology that associates the Multiple Drain pro-
cess with the Company's PowerMESHTM horizontal
layout. The resulting product has an outstanding low
on-resistance, impressively high dv/dt and excellent
avalanche characteristics. The adoption of the
Company's proprietary strip technique yields overall
dynamic performance that is significantly better than
that of similar competition's products.
APPLICATIONS
The MDmeshTM family is very suitable for increasing
power density of high voltage converters allowing
system miniaturization and higher efficiencies.
ABSOLUTE MAXIMUM RATINGS
()Pulse width limited by safe operating area
TYPE
V
DSS
R
DS(on)
I
D
STY60NM50
500V
< 0.05
60 A
Symbol
Parameter
Value
Unit
V
DS
Drain-source Voltage (V
GS
= 0)
500
V
V
DGR
Drain-gate Voltage (R
GS
= 20 k
)
500
V
V
GS
Gate- source Voltage
30
V
I
D
Drain Current (continuous) at T
C
= 25C
60
A
I
D
Drain Current (continuous) at T
C
= 100C
37.8
A
I
DM
(
l
)
Drain Current (pulsed)
240
A
P
TOT
Total Dissipation at T
C
= 25C
560
W
V
ESD(G-S)
Gate source ESD(HBM-C=100pF, R=15K
)
6
KV
Derating Factor
4.5
W/C
dv/dt (1)
Peak Diode Recovery voltage slope
15
V/ns
T
stg
Storage Temperature
65 to 150
C
T
j
Max. Operating Junction Temperature
150
C
(1)I
SD
60A, di/dt
400A/s, V
DD
V
(BR)DSS
, T
j
T
JMAX
Max247
1
2
3
INTERNAL SCHEMATIC DIAGRAM
STY60NM50
2/8
THERMAL DATA
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED)
OFF
ON
(1)
DYNAMIC
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
Rthj-case
Thermal Resistance Junction-case Max
0.22
C/W
Rthj-amb
Thermal Resistance Junction-ambient Max
30
C/W
T
l
Maximum Lead Temperature For Soldering Purpose
300
C
Symbol
Parameter
Max Value
Unit
I
AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
j
max)
30
A
E
AS
Single Pulse Avalanche Energy
(starting T
j
= 25 C, I
D
= I
AR
, V
DD
= 35 V)
1.4
J
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
(BR)DSS
Drain-source
Breakdown Voltage
I
D
= 250 A, V
GS
= 0
500
V
I
DSS
Zero Gate Voltage
Drain Current (V
GS
= 0)
V
DS
= Max Rating
10
A
V
DS
= Max Rating, T
C
= 125 C
100
A
I
GSS
Gate-body Leakage
Current (V
DS
= 0)
V
GS
= 20V
10
A
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250A
3
4
5
V
R
DS(on)
Static Drain-source On
Resistance
V
GS
= 10V, I
D
= 30A
0.045
0.05
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
g
fs
(1)
Forward Transconductance
V
DS
> I
D(on)
x R
DS(on)max,
I
D
= 30A
35
S
C
iss
Input Capacitance
V
DS
= 25V, f = 1 MHz, V
GS
= 0
7500
pF
C
oss
Output Capacitance
980
pF
C
rss
Reverse Transfer
Capacitance
200
pF
R
G
Gate Input Resistance
f=1 MHz Gate DC Bias = 0
Test Signal Level = 20mV
Open Drain
1.5
3/8
STY60NM50
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
SWITCHING OFF
SOURCE DRAIN DIODE
Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
d(on)
Turn-on Delay Time
V
DD
= 250V, I
D
= 30A
R
G
= 4.7
V
GS
= 10V
(see test circuit, Figure 3)
51
ns
t
r
Rise Time
58
ns
Q
g
Total Gate Charge
V
DD
= 400V, I
D
= 60A,
V
GS
= 10V
190
266
nC
Q
gs
Gate-Source Charge
53
nC
Q
gd
Gate-Drain Charge
97
nC
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t
r(Voff)
Off-voltage Rise Time
V
DD
= 400V, I
D
= 60A,
R
G
= 4.7
,
V
GS
= 10V
(see test circuit, Figure 5)
51
ns
t
f
Fall Time
46
ns
t
c
Cross-over Time
108
ns
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
I
SD
Source-drain Current
60
A
I
SDM
(2)
Source-drain Current (pulsed)
240
A
V
SD
(1)
Forward On Voltage
I
SD
= 60A, V
GS
= 0
1.5
V
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 60A, di/dt = 100A/s,
V
DD
= 100 V, T
j
= 25C
(see test circuit, Figure 5)
532
9.9
37
ns
C
A
t
rr
Q
rr
I
RRM
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
I
SD
= 60A, di/dt = 100A/s,
V
DD
= 100 V, T
j
= 150C
(see test circuit, Figure 5)
636
13.4
42
ns
C
A
Safe Operating Area
Thermal Impedance
STY60NM50
4/8
Transconductance
Output Characteristics
Static Drain-source On Resistance
Transfer Characteristics
Gate Charge vs Gate-source Voltage
Capacitance Variations
5/8
STY60NM50
Normalized Gate Threshold Voltage vs Temp.
Source-drain Diode Forward Characteristics
Normalized On Resistance vs Temperature
STY60NM50
6/8
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
7/8
STY60NM50
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.70
5.30
A1
2.20
2.60
b
1.00
1.40
b1
2.00
2.40
b2
3.00
3.40
c
0.40
0.80
D
19.70
20.30
e
5.35
5.55
E
15.30
15.90
L
14.20
15.20
L1
3.70
4.30
P025Q
Max247 MECHANICAL DATA
STY60NM50
8/8
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2002 STMicroelectronics - Printed in Italy - All Rights Reserved
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