TDA7319

3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR

ONE STEREO INPUT
ONE STEREO OUTPUT
TWO INDEPENDENT VOLUME CONTROL IN
1.0dB STEPS
TREBLE, MIDDLE AND BASS CONTROL IN
1.0dB STEPS
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I

CBUS

DESCRIPTION

The TDA7319 is a volume and tone (bass , mid-
dle and treble) processor for quality audio appli-
cation in car radio and Hi-Fi system.
Control is accomplished by serial I

C bus micro-

processor interface.
The AC signal setting is obtained by resistor net-
works and switches combined with operational
amplifiers.

Thanks to the used BIPOLAR/MOS Technology,
Low Distortion, Low Noise and Low Dc stepping
are obtained.

May 1995

C1 2.2

C2 2.2

1st VOL

TREBLE

SERIAL BUS DECODE & LATCHES

MIDDLE

BASS

2nd VOL

MIDDLE

BASS

SUPPLY

OUT L

SCL

SDA

DIGGND

OUT R

TREBLE(R)

MOUT(R)

MIN(R)

BOUT(R)

BIN(L)

5.6nF

15nF

22nF

C11

100nF

C12

100nF

CREF

AGND

CREF

BUS

5.6nF

MOUT(L)

TREBLE(L)

MIN(L)

BOUT(L)

BIN(L)

15nF

22nF

100nF

C10

100nF

2.7K

5.6K

2.7K

5.6K

D93AU042E

BLOCK DIAGRAM AND APPLICATION CIRCUIT

ORDERING NUMBERS: TDA7319 (DIP20)

TDA7319D (SO20)

DIP20

SO20

1/16

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

Operating Supply Voltage

10.5

amb

Operating Ambient Temperature

-40 to 85

stg

Storage Temperature Range

-55 to 150

THERMAL DATA

Symbol

Parameter

DIP20

SO20

Unit

th j-amb

Thermal Resistance Junction-pins

150

C/W

QUICK REFERENCE DATA

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

10.5

Max. input signal handling

Vrms

THD

Total Harmonic Distortion V = 1Vrms f = 1KHz

0.01

0.08

S/N

Signal to Noise Ratio

106

Channel Separation f = 1KHz

100

1st and 2nd Volume Control 1dB step

-47

Bass, Middle and Treble Control 1dB step

-14

+14

Mute Attenuation

100

IN L

TREBLE L

M IN L

M OUT L

B OUT L

B IN L

OUT L

SDA

GND

OUT R

B OUT R

M OUT R

B IN R

M IN R

TREBLE R

IN R

CREF

D93AU041A

SCL

DIG GND

PIN CONNECTION

TDA7319

2/16

ELECTRICAL CHARACTERISTICS (V

= 9V; R

= 10K

; f = 1KHz; all control = flat (G = 0); T

amb

C Refer to the test circuit, unless otherwise specified.)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

INPUT

Input Resistance

1st VOLUME CONTROL

RANGE

Control Range

VMAX

Maximum Attenuation

step

Step Resolution

0.5

1.0

1.5

Attenuation Set Error

G = 0 to -24dB

-1.0

1.0

G = -24 to -47dB

-1.5

1.5

Tracking Error

G = 0 to -24dB

G = 24 to -47dB

mute

Mute Attenuation

100

DC Steps

Adiacent Attenuation Steps

From 0dB to A

VMAX

0.5

2nd VOLUME CONTROL

RANGE

Control Range

VMAX

Maximum Attenuation

step

Step Resolution

0.5

1.0

1.5

Attenuation Set Error

G = 0 to -24dB

-1.0

1.0

G = -24 to -47dB

-1.5

1.5

Tracking Error

G = 0 to -24dB

G = 24 to -47dB

MUTE

Mute Attenuation

100

DC Steps

Adiacent Attenuation Steps

From 0dB to A

VMAX

0.5

BASS

Internal Feedback Resistance

RANGE

Control Range

11.5

step

Step Resolution

0.5

1.5

MIDDLE

Internal Feedback Resistance

RANGE

Control Range

11.5

step

Step Resolution

0.5

1.5

TREBLE

RANGE

Control Range

step

Step Resolution

0.5

1.5

SUPPLY

Supply Voltage (note1)

10.5

Supply Current

SVR

Ripple Rejection

AUDIO OUTPUT

clip

Clipping Level

d = 0.3%

2.6

Vrms

Output Load Resistance

Output Impedance

100

180

300

DC Voltage Level

3.8

TDA7319

3/16

ELECTRICAL CHARACTERISTICS (continued)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

GENERAL

Output Noise

All Gains 0dB (B = 20 to 20kHz flat)

Total Tracking Error

= 0 to -24dB

= -24 to -47dB

S/N

Signal to Noise Ratio

All Gains = 0dB; V

= 1V

rms

106

Channel Separation

100

Distortion

= 0; V

= 1V

rms

0.01

0.08

BUS INPUTS

Input Low Voltage

Input High Voltage

Input Current

= 0.4V

-5

Output Voltage SDA
Acknowledge

= 1.6mA

0.4

0.8

Note 1: the device is functionally good at Vs = 5V. A step down, on V

, to 4V does't reset the device.

APPLICATION SUGGESTIONS
The first and the last stages are volume control
blocks. The control range is 0 to -47dB (mute)
with a 1dB step.
The very high resolution allows the implementation
of systems free from any noisy acoustical effect.
The TDA7319 audioprocessor provides 3 bands
tones control.

Bass, Middle Stages
The Bass and the middle cells have the same
structure.
The Bass cell has an internal resistor Ri = 44K

typical.
The Middle cell has an internal resistor Ri = 25K

typical.
Several filter types can be implemented, connect-
ing external components to the Bass/Middle IN
and OUT pins.

The fig.1 refers to basic T Type Bandpass Filter
starting from the filter component values (R1 in-
ternal and R2,C1,C2 external) the centre fre-
quency Fc, the gain Av at max. boost and the fil-
ter Q factor are computed as follows:

Ri, R2, C1, C2

R2 C2

R2 C1

Ri C1

R2 C1

R2 C2

Ri R2

C1 C2

R2 C1

R2 C2

Viceversa, once Fc, Av, and Ri internal value are
fixed, the external components values will be:

1 Q

(

)

Treble Stage
The treble stage is a high pass filter whose time
constant is fixed by an internal resistor (25K

typical) and an external capacitor connected be-
tween treble pins and ground
Typical responses are reported in Figg. 10 to 13.

CREF

The suggested 10

F reference capacitor (CREF)

value can be reduced to 4.7

F if the application

requires faster power ON.

Ri internal

OUT

D95AU313

Figure 1.

TDA7319

4/16

Timing Diagram of I

CBUS

Data Validity on the I

CBUS

C BUS INTERFACE

Data transmission from microprocessor to the
TDA7319 and viceversa takes place thru the 2
wires I

C BUS interface, consisting of the two

lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).

Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.

Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.

Acknowledge
The master (

P) puts a resistive HIGH level on the

SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.

The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.

Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the

P can use a simplier transmis-

sion: simply it generates the 9th clock pulse with-
out checking the slave acknowledging, and then
sends the new data.

This approach of course is less protected from
misworking and decreases the noise immunity.

Acknowledge on the I

CBUS

TDA7319

7/16

SDA, SCL I

CBUS TIMING

Symbol

Parameter

Min.

Typ.

Max.

Unit

SCL

SCL clock frequency

400

kHz

BUF

Bus free time between a STOP and START condition

1.3

HD:STA

Hold time (repeated) START condition. After this period, the first
clock pulse is generated

0.6

LOW

LOW period of the SCL clock

1.3

HIGH

HIGH period of the SCL clock

0.6

SU:STA

Set-up time for a repeated START condition

0.6

HD:DA

Data hold time

0.300

SU:DAT

Data set-up time

100

Rise time of both SDA and SCL signals

300

ns (*)

Fall time of both SDA and SCL signals

300

ns (*)

SU:STO

Set-up time for STOP condition

0.6

All values referred to V

IH min.

and V

IL max.

levels

(*) Must be guaranteed by the I

C BUS master.

SDA

SCL

BUF

HD;STA

LOW

HD;DAT

SU;DAT

HIGH

SU;STA

HD;STA

SU;STO

D95AU314

P = STOP
S = START

Definition of timing on the I

C-bus

TDA7319

8/16

MSB

LSB

1st VOLUME

2nd VOLUME

TREBLE

MIDDLE

BASS

MUTMUX

POWER ON RESET:
1st volume = 2nd volume = Mute
Treble = Middle = Bass = -14dB
Mutmux = Active Input

FUNCTION CODES

TDA7319 ADDRESS

MSB

first byte

LSB

MSB

LSB

MSB

LSB

ACK

DATA

ACK

DATA

ACK

Data Transferred (N-bytes + Acknowledge)

ACK = Acknowledge
S = Start
P = Stop

MAX CLOCK SPEED 400kbits/s

SOFTWARE SPECIFICATION

Chip address

MSB

LSB

SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:

A start condition (s)
A chip address byte, containing the TDA7319

address (the 8th bit of the byte must be 0). The
TDA7319 must always acknowledge at the end
of each transmitted byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)

TDA7319

9/16

MSB

LSB

FUNCTION

step 1dB

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

step 8dB

0dB

-8dB

-16dB

-24dB

-32dB

-40dB

MUTE

1st VOLUME CODES

MSB

LSB

FUNCTION

step 1dB

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

step 8dB

0dB

-8dB

-16dB

-24dB

-32dB

-40dB

MUTE

2nd VOLUME CODES

TDA7319

10/16

MSB

LSB

FUNCTION

TREBLE BOOST

0dB

1dB

2dB

3dB

4dB

5dB

6dB

7dB

8dB

9dB

10dB

11dB

12dB

13dB

14dB

TREBLE CUT

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

-8dB

-9dB

-10dB

-11dB

-12dB

-13dB

-14dB

TREBLE CODES

TDA7319

11/16

MSB

LSB

FUNCTION

MIDDLE BOOST

0dB

1dB

2dB

3dB

4dB

5dB

6dB

7dB

8dB

9dB

10dB

11dB

12dB

13dB

14dB

MIDDLE CUT

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

-8dB

-9dB

-10dB

-11dB

-12dB

-13dB

-14dB

MIDDLE CODES

TDA7319

12/16

MSB

LSB

FUNCTION

BASS BOOST

0dB

1dB

2dB

3dB

4dB

5dB

6dB

7dB

8dB

9dB

10dB

11dB

12dB

13dB

14dB

BASS CUT

0dB

-1dB

-2dB

-3dB

-4dB

-5dB

-6dB

-7dB

-8dB

-9dB

-10dB

-11dB

-12dB

-13dB

-14dB

BASS CODES

MSB

LSB

FUNCTION

INPUTS

NOT ALLOWED

MUTMUX CODES

TDA7319

13/16

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-
tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-
press written approval of SGS-THOMSON Microelectronics.

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TDA7319

16/16

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