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TDA7376PD
April 2004
HIGH OUTPUT POWER CAPABILITY
2 x 40W max./4
2 x 35W/4
EIAJ
2 x 25W/4
@14.4V, 1KHz, 10%
2 x 25W/2
@14.4V, 1KHz, 10%
2
DRIVING
DIFFERENTIAL INPUTS
MINIMUM EXTERNAL COMPONENTS
COUNT
INTERNALLY FIXED GAIN (26dB)
MUTE FUNCTION (CMOS COMPATIBLE)
AUTOMUTE AT MINIMUM SUPPLY VOLTAGE
DETECTION
STAND-BY FUNCTION
NO AUDIBLE POP DURING MUTE AND SY-
BY OPERATIONS
CLIPPING DETECTOR WITH
PROGRAMMABLE DISTORTION
THRESHOLD
Protections:
SHORT CIRCUIT (OUT TO GROUND, OUT TO
SUPPLY VOLTAGE, ACROSS THE LOAD)
OVERRATING CHIP TEMPERATURE WITH
SOFT THERMAL LIMITER
LOAD DUMP VOLTAGE
FORTUITOUS OPEN GROUND
LOUDSPEAKER DC CURRENT
ESD
DESCRIPTION
The TDA7376PD is a new technology dual bridge
Audio Amplifier in PowerSO36 package designed
for car radio applications. Thanks to the fully com-
plementary PNP/NPN output stage configuration
the TDA7376PD delivers a rail-to-rail voltage
swing with no need of bootstrap capacitors.
PowerSO36 (Slug up)
ORDERING NUMBER: TDA7376PD
2 X 35W POWER AMPLIFIER FOR CAR RADIO
BLOCK DIAGRAM
TDA7376PD
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DESCRIPTION (Continued)
Differential input pairs, that will accept either single ended or differential input signals, guarantee high
noise immunity making the device suitable for both car radio and car boosters applications.
The audio mute control, that attenuates the output signal of the audio amplifiers, suppresses pop on - off
transients and cuts any noises coming from previous stages. The St-By control, that de-biases the ampli-
fiers, reduces the cost of the power switch. The on-board programmable distortion detector allows com-
pression facility whenever the ampifier is overdriven, so limiting the distortion at any levels inside the
presettable range.
PIN CONNECTION (Top view)
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
Symbol
Parameter
Value
Unit
V
OP
Operating Supply Voltage
18
V
V
s
DC Supply Voltage
28
V
V
peak
Peak Supply Voltage (t = 50ms)
50
V
I
O
Output Peak Current (not repetitive t = 100
s)
8
A
Output Peak Current (repetitive f > 10Hz)
6
A
P
tot
Power Dissipation T
case
= 85C
36
W
T
stg
, T
j
Storage and Junction Temperature
-40 to 150
C
Symbol
Parameter
Value
Unit
R
th j-case
Thermal Resistance Junction to case
Max
2
C/W
TAB
SGND
ST-BY
MUTE
NC
NC
OUT1+
NC
PWGND
PWGND
18
16
17
15
6
5
4
3
2
21
22
31
32
33
35
34
36
20
1
19
NC
D02AU1348
IN1-
VCC
IN1+
9
8
7
28
29
30
VCC
10
27
OUT1-
OUT1+
OUT1-
14
12
11
23
25
26
TAB
NC
13
24
NC
PWGND
PWGND
IN2+
NC
IN2-
NC
CD-OUT
THDSET
OUT2-
VCC
VCC
OUT2-
NC
NC
OUT2+
OUT2+
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TDA7376PD
Figure 1. Differential Inputs Test and Application Circuit
Figure 2. Single Ended Inputs Test and Application Circuit
TDA7376PD
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Figure 3. Application Board Reference Circuit
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TDA7376PD
ELECTRICAL CHARACTERISTCS (Refer to the test circuits figgs 1 and 2, V
S
= 14.4V; R
L
= 4
; f = 1KHz;
T
amb
= 25C, unless otherwise specified).
(*) Saturated square wave output
(**) see figure 5 for THD setting.
The TDA7376PD is equipped with a programmable clipping distortion detector circuitry that allows to sig-
nal out the output stage saturation by providing a current sinking into an open collector output (DDout)
when the total harmonic distortion of the output signal reaches the preset level. The desired threshold is
fixed through an external divider that produces a proper voltage level across the THD set pin. Fig. 4 shows
the THD detection threshold versus the THD set voltage. Since it is essential that the THD set voltage be
proportional to the supply voltage, fig. 5 shows its value as a fraction of V
CC
. The actual voltage can be
computed by multiplying the fraction corresponding to the desired THD threshold by the application's sup-
ply voltage.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
S
Supply Voltage Range
8
18
V
I
d
Total Quiescent Drain Current
R
L
=
200
mA
V
OS
Output Offset Voltage
120
mV
P
O
Output Power
THD = 10%;
THD = 10%; R
L
= 2
23
33
25
37
W
W
P
O max
Max. Output Power (*)
36
40
W
P
O EIAJ
EIAJ Outout Power (*)
V
S
= 13.7V
32
35
W
THD
Distortion
P
O
= 0.5 to 10W
P
O
= 0.5 to 15W
0.03
0.08
%
%
C
T
Cross Talk
f = 1KHz; R
g
f = 10KHz; R
g
80
70
dB
dB
R
IN
Input Impedance
differential input
Single Ended input
45
40
K
K
G
V
Voltage Gain
differential input
25
26
27
dB
Single Ended input
25
26
27
dB
G
V
Channel Gain Balance
1
dB
E
IN
Input Noise Voltage
R
g
= 600
; "A" weighted
R
g
= 600
; 22Hz to 33KHz
3
4
6
V
V
SVR
Supply Voltage Rejection
f = 100Hz; V
r
= 1Vrms; R
g
= 0;
f = 10Hz; V
r
= 1Vrms; R
g
= 0;
45
55
dB
dB
BW
Power Bandwidth
(-3dB)
75
kHz
CMRR
Common Mode Rejection Ratio
V
CM
= 1Vrms input referred
60
dB
A
SB
Stand-by Attenuation
V
SB
= 1.5V; P
O ref
= 1W
80
90
dB
V
SB IN
Stand-by In Threshold
1.5
V
V
SB OUT
Stand-by Out Threshold
3.5
V
I
sb
Stand-by Current Consumption
V
SB
= 0V
20
A
A
M
Mute Attenuation
V
M
= 1.5V; P
Oref
= 1W
85
dB
V
M IN
Mute in Threshold
1.5
V
V
M OUT
Mute out Threshold
3.5
V
I
6
Mute pin Current
V
6
= 0 to V
S
, ; V
S max.
= 18V
100
A
D
DL
Distortion Detection Level (**)
3.5
%
D
DOUT
Distortion Detector Output DC
Current
Output low, sinked current
(
V
pin10
= 1.5V
)
1
mA
Output high, leakage current
(V
pin10
= V
S
, @ V
Smax
= 18V)
10
A
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