FOUR HIGH PASS CHANNELS
ONE STEREO LOW PASS CHANNEL WITH
GAIN CONTROL
DIRECT MUTE PIN
FULLY PROGRAMMABLE VIA I
2
C BUS
DESCRIPTION
The TDA7401 is an upgrade of the TDA7435
audioprocessor.
Due to a highly linear signal processing, using
CMOS-switching techniques very low distortion
and very low noise are obtained.
Second order high pass and low pass filters with
programmable corner frequencies provide the
loudspeaker equalization.
Very low DC stepping is obtained by using a
BICMOS technology.
January 1999
HP FILTER
HP FILTER
HP FILTER
HP FILTER
MUTE
GAIN
+20/-79dB
MUX
I
2
C BUS
SUPPLY
22
21
20
19
18
17
16
15
1
2
HP FL 1
HP FL 2
HP FR 1
HP FR 2
HP RL 1
HP RL 2
HP RR 1
HP RR 2
AUX 1 IN L
AUX 1 IN R
7
6
AUX 2 OUT R
8
AUX 2 OUT L
9
HP RR OUT
14
HP RL OUT
13
HP FR OUT
11
HP FL OUT
10
OUT REF
12
28
23
24
25
26
27
SDA SCL DGND AGND CREF
V
CC
D98AU822A
3
MUTE
4
5
CR1 CL1
CR2
CL2
BLOCK DIAGRAM
SO28
ORDERING NUMBER: TDA7401D
TDA7401
DIGITALLY CONTROLLED AUDIO PROCESSOR
WITH LOUDSPEAKERS EQUALIZER
1/10
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Operating Supply Voltage
10.5
V
T
amb
Operating Ambient Temperature
-40 to 85
C
T
stg
Storage Temperature Range
-55 to 150
C
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction-pins
65
C/W
QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
S
Supply Voltage
6
9
10.2
V
V
CL
Max. input signal handling
2.1
2.6
Vrms
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
0.08
%
S/N
Signal to Noise Ratio
106
dB
S
C
Channel Separation f = 1KHz
-80
100
dB
V
REF
Reference Voltage Output (pin 12)
4.2
4.5
4.8
V
AUX 1 IN L
AUX 1 IN R
MUTE
CR1
CL1
CR2
CL2
AUX 2 OUT R
AUX 2 OUT L
HP FR 1
HP FL 2
HP FL 1
AGND
CREF
DGND
SCL
SDA
V
CC
1
3
2
4
5
6
7
8
9
26
25
24
23
22
20
21
19
27
10
28
HP FL OUT
HP FR 2
D98AU823A
HP FR OUT
OUT REF
HP RL OUT
HP RR 1
HP RL 2
HP RL 1
11
12
13
18
16
17
15
14
HP RR OUT
HP RR 2
PIN CONNECTION
TDA7401
2/10
ELECTRICAL CHARACTERISTICS (V
S
= 9V; R
L
= 10K
; R
g
= 50
; T
amb
= 25
C; all gains = 0dB;
f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
INPUT STAGE: AUX1
R
I
Input Resistance
37.5
50
62.5
K
V
CL
Clipping Level
d
0.3%
2.1
2.6
V
RMS
S
I
Input Separation
80
100
dB
GAIN CONTROL
G
MAX
Maximum Input Gain
20
dB
A
MAX
Maximum Attenuation
79
dB
A
STEP
Step Resolution
0.5
1
1.5
dB
E
A
Attenuation Set Error
G = -20 to +20dB
-1.25
0
+1.25
dB
G = -60 to -20dB
-4
3
dB
E
T
Tracking Error
2
dB
V
DC
DC Steps
Adiacent Attenuation Steps
0.1
3
mV
From 0dB to G
MIN
0.5
5
mV
AUDIO OUTPUT (Pin 8 - 9, 10 - 14)
V
clip
Clipping Level
d = 0.3%
2.1
2.6
Vrms
R
L
Output Load Resistance
AC coupled
2
K
R
O
Output Impedance
30
100
V
DC
DC Voltage Level
4.2
4.5
4.8
V
STAGE: HP FILTER
R1
Resistance at pin HP1
HIGHPASS BYTE = XXXX1000
127.5
170
212.5
K
R2
Resistance at pin HP2
1
M
V
CL
Clipping Level
d
0.3%
2.1
2.6
Vrms
MUTE
A
MUTE
Mute Attenuation
80
100
dB
V
THM
Mute Threshold
1.2
1.7
2.2
V
R
INT
Pullup Resistor (pin 3)
(note 1)
37.5
50
62.5
K
GENERAL
V
CC
Supply Voltage
6
9
10.2
V
I
CC
Supply Current
7
8
9
mA
PSRR
Power Supply Rejection Ratio
f = 1KHz
60
70
dB
e
NO
Output Noise
Non Inverting Output Muted (B =
20 to 20kHz flat)
3.5
15
V
All Gains 0dB (B = 20 to 20kHz
flat)
5
15
V
S/N
Signal to Noise Ratio
All Gains = 0dB; V
O
= 1V
rms
106
dB
S
C
Channel Separation
80
100
dB
d
Distortion
V
IN
=1V
0.01
0.08
%
BUS INPUTS
V
IL
Input Low Voltage
0.8
V
V
lH
Input High Voltage
2.5
V
I
lN
Input Current
V
IN
= 0.4V
-5
5
A
V
O
Output Voltage SDA
Acknowledge
I
O
= 1.6mA
0.1
0.4
V
Note 1: Internal pullup resistor to 3.3V; "LOW" = mute active
TDA7401
3/10
100nF
100nF
+
-
HP2
HP1
R1 = EQUIVALENT RESISTANCE AT PIN HP1
R2 = EQUIVALENT RESISTANCE AT PIN HP2
D98AU836
56.5K
18.7K
9.4K
7.7K
4.4K
3.6K
12.5K
56K
6.2K
3.5K
2.1K
3.8K
4.7K
9.4K
28K
28K
Figure 1. HP Filter
HP FILTER
HP FILTER
HP FILTER
HP FILTER
MUTE
GAIN
+20/-79dB
MUX
I
2
C BUS
SUPPLY
22
21
20
19
18
17
16
15
1
2
HP FL 1
HP FL 2
HP FR 1
HP FR 2
HP RL 1
HP RL 2
HP RR 1
HP RR 2
AUX 1 IN L
AUX 1 IN R
7
6
AUX R OUT
8
AUX L OUT
9
HP RR OUT
14
HP RL OUT
13
HP FR OUT
11
HP FL OUT
10
OUT REF
12
28
23
24
25
26
27
SDA
SCL
DGND
AGND
CREF
V
CC
D98AU835
3
MUTE
4
5
CR1
CL1
CR2
CL2
100nF 100nF
HP FL IN
100nF 100nF
HP FR IN
100nF 100nF
HP RL IN
100nF 100nF
HP RR IN
220nF
AUX L IN
220nF
AUX R IN
100nF
100
nF
100
nF
100nF
AUX R OUT
AUX L OUT
HP RR OUT
HP RL OUT
HP FR OUT
HP FL OUT
OUT REF
100nF
10
F
V
CC
10
F
P
Figure 2. Application Circuit
TDA7401
4/10
Figure 4. Timing Diagram of I
2
CBUS
Figure 3. Data Validity on the I
2
CBUS
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7401 and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 2, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.3 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 4). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse time.
In this case the master transmitter can generate
the STOP information in order to abort the transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
P can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 5. Acknowledge on the I
2
CBUS
TDA7401
5/10
MSB
LSB
FUNCTION
X
X
X
I
X
D2
D1
D0
0
0
0
Not used
0
0
1
Mode
0
1
0
Gain AUX 1 L
0
1
1
Gain AUX 1 R
1
0
0
High Pass Filter FL
1
0
1
High Pass Filter FR
1
1
0
High Pass Filter RL
1
1
1
High Pass Filter RR
AUTO INCREMENT
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled
SUBADDRESS (receive mode)
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte,(the LSB bit determines
read/write transmission)
A subaddress byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
LSB
MSB
LSB
MSB
LSB
S
1
0
0
0
1
0
1
R/W
ACK
X
X
X
I
X A2 A1 A0
ACK
DATA
ACK
P
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used
TDA7401
6/10
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
X
High Pass Mute ON
1
High Pass Mute OFF
0
AUX1 Input Mute ON
1
AUX1 Input Mute OFF
0
AUX2 Inverted Output
1
AUX2 Non Inv. Output
AUX 2 Output Selection
0
0
High Pass Filter Front
0
1
High Pass Filter Rear
1
0
Aux 1 Input
1
1
Mute
AUX1 Low Pass Filter
(C1 = C2 = 100nF)
0
0
Flat
0
1
120Hz
1
0
80Hz
1
1
50Hz
GAIN AUX1L, AUX1R
MSB
LSB
GAIN AUX1L, R
D7
D6
D5
D4
D3
D2
D1
D0
1
:
1
1
1
:
1
1
0
0
:
0
0
:
0
0
X
0
:
0
0
0
:
0
0
0
0
:
0
0
:
1
1
1
0
:
0
0
0
:
0
0
0
0
:
0
0
:
0
0
1
1
:
1
1
0
:
0
0
0
0
:
0
1
:
0
0
X
1
:
0
0
1
:
0
0
0
0
:
1
0
:
1
1
X
1
:
0
0
1
:
0
0
0
0
:
1
0
:
1
1
X
1
:
0
0
1
:
0
0
0
0
:
1
0
:
1
1
X
1
:
1
0
1
:
1
0
0
1
:
1
0
:
0
1
X
+31dB
:
+17dB
+16dB
+15dB
:
+1dB
0dB
0dB
-1dB
:
-15dB
-16dB
:
-78dB
-79dB
Mute
Note: Is is not recommended to use a gain more than 20dB for system performance reason. In general, the max. gain should be limited by
software to the maximum value, which is needed for the system.
MODE
TDA7401
7/10
MSB
LSB
FL, FR, RL, RR
D7
D6
D5
D4
D3
D2
D1
D0
2nd order HP Filter Mode
(C1 = C2 = 100nF)
X
X
X
X
0
0
0
0
f
c
= 40Hz
0
0
0
1
f
c
= 60Hz
0
0
1
0
f
c
= 80Hz
0
0
1
1
f
c
= 100Hz
0
1
0
0
f
c
= 120Hz
0
1
0
1
f
c
= 150Hz
0
1
1
0
f
c
= 180Hz
0
1
1
1
f
c
= 220Hz
First order HP Flat Mode
1
0
0
0
f
c
= 9Hz
HIGH PASS FILTERS
TDA7401
8/10
SO28
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.65
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
0.020
c1
45
(typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
8
(max.)
OUTLINE AND
MECHANICAL DATA
TDA7401
9/10
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics Printed in Italy All Rights Reserved
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TDA7401
10/10
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