TDA7435
DIGITALLY CONTROLLED AUDIO PROCESSOR
WITH LOUDSPEAKERS EQUALIZER
INPUT
- FOUR HIGH PASS CHANNELS
- TWO AUX STEREO CHANNELS
VOLUME CONTROL IN 1dB STEPS WITH
GAIN UP TO 15dB
SOFT MUTE AND DIRECT MUTE
FOUR AUXILIARY CHANNELS:
- TWO SPEAKERS CONTROL IN 1dB STEP
- TWO CHANNELS MULTIPLEXED WITH
THE HIGH PASS CHANNELS
ALL FUNCTIONS PROGRAMMABLE VIA SE-
RIAL I
2
CBUS
DESCRIPTION
The audioprocessor TDA7435 is an upgrade of
the TDA731X audioprocessor family.
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained.
A second programmable high pass filtering pro-
vides the loudspeakers equalization.
The soft Mute function is implemented andcan be
activated in two ways:
1 Via serial bus (Mute byte, bit D0)
2 Directly on pin 3 through an I/O line of the mi-
crocontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
November 1996
ORDERING NUMBER: TDA7435D
SO28
HP FILTER
HP FILTER
HP FILTER
HP FILTER
SOFT
MUTE
GAIN
0-15dB/1dB step
MUX
ATTENUATOR
0/-79dB
ATTENUATOR
0/-79dB
I
2
C BUS
SUPPLY
22
21
20
19
18
17
16
15
6
7
1
2
HP FL 1
HP FL 2
HP FR 1
HP FR 2
HP RL 1
HP RL 2
HP RR 1
HP RR 2
AUX 2 IN L
AUX 2 IN R
AUX 1 IN L
AUX 1 IN R
AUX 1 OUT R
4
AUX 1 OUT L
5
AUX 2 OUT R
8
AUX 2 OUT L
9
HP RR OUT
14
HP RL OUT
13
HP FR OUT
11
HP FL OUT
10
OUT REF
12
28
23
24
25
26
27
SDA SCL DGND AGND CREF
V
CC
D96AU437A
3
CSM
BLOCK DIAGRAM
1/10
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Operating Supply Voltage
10.5
V
T
amb
Operating Ambient Temperature
-40 to 85
C
T
stg
Storage Temperature Range
-55 to 150
C
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th j-amb
Thermal Resistance Junction-pins
65
C/W
QUICK REFERENCE DATA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
S
Supply Voltage
6
9
10.2
V
V
CL
Max. input signal handling
2.1
2.6
Vrms
THD
Total Harmonic Distortion V = 1Vrms f = 1KHz
0.01
0.08
%
S/N
Signal to Noise Ratio
106
dB
S
C
Channel Separation f = 1KHz
80
dB
Input Gain AUX1 1dB step
0
15
dB
AUX 1 IN L
AUX 1 IN R
CSM
AUX 1 OUT R
AUX 1 OUT L
AUX 2 IN R
AUX 2 IN L
AUX 2 OUT R
AUX 2 OUT L
HP FR 1
HP FL 2
HP FL 1
AGND
CREF
DGND
SCL
SDA
V
CC
1
3
2
4
5
6
7
8
9
26
25
24
23
22
20
21
19
27
10
28
HP FL OUT
HP FR 2
D96AU438
HP FR OUT
OUT REF
HP RL OUT
HP RR 1
HP RL 2
HP RL 1
11
12
13
18
16
17
15
14
HP RR OUT
HP RR 2
PIN CONNECTION
TDA7435
2/10
ELECTRICAL CHARACTERISTICS (V
S
= 9V; R
L
= 10K
; R
g
= 50
; T
amb
= 25
C; all gains = 0dB;
f = 1KHz. Refer to the test circuit, unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
INPUT STAGE: AUX1
R
I
Input Resistance
24
33
42
K
V
CL
Clipping Level
d
0.3%
2.1
2.6
V
RMS
S
I
Input Separation
70
80
dB
G
I MIN
Minimum Input Gain
-0.75
0
0.75
dB
G
I MAX
Maximum Input Gain
13.75
15
16.25
dB
G
step
Step Resolution
0.5
1.0
1.5
dB
E
a
Set Error
-1.25
0
1.25
dB
V
DC
DC Steps
Adiacent Gain Steps
0.5
10
mV
G
IIN
to G
IMAX
2.5
mV
SPEAKER ATTENUATORS - AUX 1
C
RANGE
Control Range
79
dB
A
step
Step Resolution
Av = 0 to -40dB
0.5
1
1.5
dB
A
MUTE
Output Mute Attenuation
Data Word = 1111XXXX
80
105
dB
E
A
Attenuation Set Error
Av = 0 to -40dB
1.5
dB
V
DC
DC Steps
Adjacent Attenuation Steps
0
3
mV
AUDIO OUTPUT (Pin 4 - 5, 8 - 9, 10 - 14)
V
clip
Clipping Level
d = 0.3%
2.1
2.6
Vrms
R
L
Output Load Resistance
2
K
R
O
Output Impedance
20
30
100
V
DC
DC Voltage Level
3.5
3.8
4.1
V
STAGE: AUX2
R
I
Input Resistance
24
33
42
K
V
CL
Clipping Level
2.1
2.6
Vrms
S
I
Input Separation
70
80
dB
G
I
Gain
-0.75
0
0.75
dB
Input Mute
80
100
dB
STAGE: HP FILTER
R1
Resistance at pin HP1
HIGHPASS BYTE
D3 = 1
XXXX1XXX
120
170
220
K
R2
Resistance at pin HP2
1
M
V
CL
Clipping Level
d
0.3%
2.1
2.6
Vrms
SOFT MUTE
A
MUTE
Mute Attenuation
40
50
dB
T
DON
ON Delay Time
C
CSM
= 22nF; 0 to -20dB; I = I
MAX
0.7
1
2
ms
C
CSM
= 22nF; 0 to -20dB; I = I
MIN
10
30
50
ms
T
DOFF
OFF Current
V
CSM
= 0V; I = I
MAX
60
160
A
V
CSM
= 0V; I = I
MIN
110
210
A
TDA7435
3/10
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
V
THSM
Soft Mute Threshold
2.3
V
R
INT
Pullup Resistor (pin 3)
(note 2)
100
K
V
SMH
(pin 3) Level High
3.5
V
V
SML
(pin 3) Level Low
Soft Mute Active
1
V
GENERAL
V
CC
Supply Voltage
6
9
10.2
V
I
CC
Supply Current
7
11
15
mA
PSRR
Power Supply Rejection Ratio
f = 1KHz
60
70
dB
e
NO
Output Noise
Output Muted (B = 20 to 20kHz flat)
3.5
V
All Gains 0dB (B = 20 to 20kHz flat)
5
15
V
S/N
Signal to Noise Ratio
All Gains = 0dB; V
O
= 1V
rms
106
dB
S
C
Channel Separation
70
80
dB
d
Distortion
V
IN
=1V
0.01
0.08
%
BUS INPUTS
V
IL
Input Low Voltage
1
V
V
lN
Input High Voltage
3
V
I
lN
Input Current
VIN = 0.4V
-5
5
A
V
O
Output Voltage SDA
Acknowledge
I
O
= 1.6mA
0.4
V
Note 1: WIN represents the MUTE programming bit pair D
6
, D
5
for the zero crossing window threshold
Note 2: Internall pullup resistor to Vs/2; "LOW" = softmute active
100nF
100nF
+
-
HP2
HP1
R1 = EQUIVALENT RESISTANCE AT PIN HP1
R2 = EQUIVALENT RESISTANCE AT PIN HP2
D96AU439
56K
18.7K
9.3K
7.6K
4.3K
3.5K
52.5K
56K
6.2K
3.5K
2.1K
3.8K
4.6K
9.3K
28K
28K
Figure 1: HP Filter.
TDA7435
4/10
Figure 3: Timing Diagram of I
2
CBUS
Figure 2: Data Validity on the I
2
CBUS
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7435 and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
Data Validity
As shown in fig. 2, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.3 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
A STOP conditions must be sent before each
START condition.
Byte Format
Every byte transferred to the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledge bit. The MSB is transferred first.
Acknowledge
The master (
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 4). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the reception
of each byte, otherwise the SDA line remains at the
HIGH level during the ninth clock pulse time. In this
case the master transmitter can generate the
STOP information in order to abort the transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
P can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreases the noise immunity.
Figure 4: Acknowledge on the I
2
CBUS
TDA7435
5/10
MSB
LSB
FUNCTION
X
X
X
I
X
D2
D1
D0
0
0
0
Mux & Gain
0
0
1
Mute
0
1
0
Speaker Attenuator AUX 1 L
0
1
1
Speaker Attenuator AUX 1 R
1
0
0
High Pass Filter FL
1
0
1
High Pass Filter FR
1
1
0
High Pass Filter RL
1
1
1
High Pass Filter RR
AUTO INCREMENT
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled
SUBADDRESS (receive mode)
TRANSMITTED DATA
Send Mode
MSB
LSB
X
X
X
X
X
SM
X
X
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chipaddress.
SOFTWARE SPECIFICATION
Interface Protocol
The interface protocol comprises:
A start condition (s)
A chip address byte,(the LSB bit determines
read/write transmission)
A subaddress byte.
A sequence of data (N-bytes + acknowledge)
A stop condition (P)
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
LSB
MSB
LSB
MSB
LSB
S
1
0
0
0
1
0
1
R/W
ACK
X
X
X
I
X A2 A1 A0
ACK
DATA
ACK
P
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used
MAX CLOCK SPEED 500kbits/s
TDA7435
6/10
DATA BYTE SPECIFICATION
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
AUX 1 Input Gain
0
0
0
0
0dB
0
0
0
1
1dB
0
0
1
0
2dB
0
0
1
1
3dB
0
1
0
0
4dB
0
1
0
1
5dB
0
1
1
0
6dB
0
1
1
1
7dB
1
0
0
0
8dB
1
0
0
1
9dB
1
0
1
0
10dB
1
0
1
1
11dB
1
1
0
0
12dB
1
1
0
1
13dB
1
1
1
0
14dB
1
1
1
1
15dB
AUX 2 Output Selection
0
0
High Pass Filter Front
0
1
High Pass Filter Rear
1
0
Aux 2 Input
1
1
Mute
MUX & GAIN
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Soft mute - SLOW SLOPE
0
1
Soft mute - FAST SLOPE
0
Soft mute ON
1
Soft mute OFF
0
0
AUX 1 Input Mute Enabled
1
0
AUX 1 Input Mute Disabled
Mute
TDA7435
7/10
MSB
LSB
AUX 1 L, R
D7
D6
D5
D4
D3
D2
D1
D0
-1dB STEPS
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
-8dB STEPS
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
0
1
1
0
-48dB
0
1
1
1
-56dB
1
0
0
0
-64dB
1
0
0
1
-72dB
1
0
0
MUTE
1
0
1
1
1
1
Speaker
MSB
LSB
FL, FR, RL, RR
D7
D6
D5
D4
D3
D2
D1
D0
2nd order HP Filter Mode
(C1 = C2 = 100nF)
0
0
0
0
f
c
= 40Hz
0
0
0
1
f
c
= 60Hz
0
0
1
0
f
c
= 80Hz
0
0
1
1
f
c
= 100Hz
0
1
0
0
f
c
= 120Hz
0
1
0
1
f
c
= 150Hz
0
1
1
0
f
c
= 180Hz
0
1
1
1
f
c
= 220Hz
First order HP Flat Mode
1
f
c
= 9Hz
HIGH PASS FILTERS
TDA7435
8/10
SO28 PACKAGE MECHANICAL DATA
DIM.
mm
inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.65
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
0.020
c1
45
(typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
8
(max.)
TDA7435
9/10
Purchase of I
2
C Components of SGS-THOMSON Microlectronics, conveys a license under the Philips
I
2
C Patent Rights to use these components in an I
2
C system, provided that the system conforms to
the I
2
C Standard Specifications as defined by Philips.
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as criticalcomponents in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1996 SGS-THOMSON Microelectronics Printed in Italy All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
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TDA7435
10/10
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