TDA9102F
H/V PROCESSOR FOR TTL V.D.U
May 1994
POWERDIP20 (0.4)
(Plastic package)
ORDER CODES : TDA9102F
HORIZONTAL SECTION
.
SYNCHRONIZATION INPUT : TTL COMPAT-
IBLE, NEGATIVE EDGE TRIGGERED
.
SYNCHRONIZATION INDEPENDENT FROM
DUTY CYCLE TIME
.
OSCILLATOR : FREQUENCY RANGE FROM
15kHz to 100kHz
.
HORIZONTAL OUTPUT PULSE SHAPER
AND SHIFTER
.
PHASE COMPARATOR BETWEEN SYN-
CHRO AND OSCILLATOR (PLL1)
.
PHASE COMPARATOR BETWEEN FLYBACK
AND OSCILLATOR (PLL2)
.
INTERNAL VOLTAGE REGULATOR
.
DC COMPATIBLE CONTROLS FOR PHASE
AND FREQUENCY
.
HORIZONTAL OUTPUT DUTY CYCLE : 48%
VERTICAL SECTION
.
SYNCHRONIZATION INPUT : TTL COMPAT-
IBLE, NEGATIVE EDGE TRIGGERED
.
SYNCHRONIZATION INDEPENDENT FROM
DUTY CYCLE TIME
.
OSCILLATOR : FREQUENCY RANGE FROM
30Hz to 120Hz
.
RAMP GENERATOR WITH VARIABLE GAIN
STAGE
.
VERTICAL RAMP VOLTAGE REFERENCE
.
INTERNAL VOLTAGE REGULATOR
.
DC COMPATIBLE CONTROLS FOR FRE-
QUENCY, AMPLITUDE AND LINEARITY
DESCRIPTION
The TDA9102F is a monolithic integrated circuit for
horizontal and vertical sync processing in mono-
chrome and color video displays driven by input
TTL compatible signals.
The TDA9102F is supplied in a 20 pin dual in line
package with pin 11 connected to ground and used
for heatsinking.
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
Horizontal Phase Adjust
Phase Comparator 2 Output
Horizontal Flyback Input
Horizontal Output
Horizontal Power Ground
C5
Horizontal TTL Input
Phase Comparator 1 Output
C2
R1
Substrate Ground
Vertical Frequency Preset
C13
Vertical TTL Input
Vertical Ramp Output
Vertical Amplitude Adjust
Vertical Linearity Adjust
Linearity Output
Vertical Reference Voltage
V
S
91
02
F
-
01
.
E
P
S
PIN CONNECTIONS
1/7
91
02
F
-
0
2
.
E
P
S
BLOCK DIAGRAM
4
15
5
69
8
1
4
17
18
16
13
12
10
3
1
2
1
1
20
19
H
O
R
IZO
N
T
A
L
F
L
Y
B
ACK
IN
PU
T
V
E
R
TIC
AL
SY
N
C
.
INPUT
D
C
V
E
R
TIC
AL
L
I
N
E
AR
ITY
ADJ
U
S
T
E
M
ENT
D
C
F
R
E
Q
UE
NC
Y
PRESET
DC V
E
R
T
I
C
A
L
AM
PL
IT
U
D
E
A
D
J
U
ST
E
M
EN
T
D
C
F
R
E
Q
UE
NC
Y
A
D
J
U
S
T
EM
ENT
D
C
H
O
R
IZO
N
T
AL
PHASE
ADJ
U
S
T
E
M
ENT
HO
R
I
Z
O
NT
A
L
SYNC.
INPUT
+ 5V
+ 5
V
V
S
V
RE
F
T
DA9102F
V
S
VOLTA
G
E
REGU
LA
TO
R
VE
R
T
I
C
AL
OS
C
I
L
L
A
T
OR
2
PH
A
S
E
CO
M
PAR
ATO
R
VE
R
T
I
C
AL
TT
L
I
N
T
E
R
F
A
C
E
LO
W
S
U
PP
LY
VO
L
T
AG
E
PR
O
T
E
C
TI
ON
HO
RI
Z
O
NTAL
OS
CI
L
L
AT
O
R
1
PHA
S
E
CO
M
P
AR
ATOR
HO
RI
Z
O
NTA
L
TTL I
N
TE
RF
A
C
E
HO
R.
PUL
S
E
SH
AP
ER
R3
C3
C1
R2
R1
C2
R1
2
R1
8
C1
8
C1
3
C9
R8
R1
4
7
C5
R4
TDA9102F
2/7
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
S
Supply Voltage
18
V
V
SYNC
Sync Input Peak Voltage
+ V
S
V
I
OH
Output Sinking Peak Current (Pin 7 ; t < 3
s)
2
A
I
15
Output Current (Pin 15)
- 10
mA
I
19
Output Current (Pin 19)
- 10
mA
P
tot
Total power dissipation
q
T
amb
< 70
o
C
q
T
pin
< 90
o
C
1.4
1.5
W
W
T
stg
, T
j
Storage and Junction Temperature
- 40 to 150
o
C
91
02F
-
0
1.
T
B
L
THERMAL DATA
Symbol
Parameter
Value
Unit
R
th(j-c)
Junction-case Thermal Resistance
40
o
C/W
R
th(j-a)
Junction-ambient Thermal Resistance
55
o
C/W
910
2F
-
0
2.
T
B
L
ELECTRICAL CHARACTERISTICS
(T
amb
= 25
o
C, V
S
= 12V, refer to the test circuits, unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
HORIZONTAL SECTION
V
S
Supply Voltage Range
10.5
12
15.5
V
I
S
Supply Current
40
70
mA
V
1
Voltage Reference at Pin 1
I
1
= 0.5mA
3.2
3.5
3.8
V
I
1
Current at Pin 1
- 1
mA
V
2
Voltage Swing at Pin 2
3.7
4
4.3
V
PP
K
0
Free Running Frequency Constant
f
o
= 1/(K
0
x R1 x C2)
3.7
4
4.3
V
3
- V
1
Control Voltage Range
(See technical note 1)
1.6
2.5
V
I
3
Peak Control Current
3
mA
K
3
Gain Phase Comparator
1
K
3
= 2 x I
3
/ 360
17
A
degree
V
4
Sync Threshold Input (neg. edge)
q
Sync high
q
Sync low
2
8
0.8
V
V
I
4
Current at Pin 4
q
Input high
q
Input low
- 10
10
A
A
T
4
Input Pulse Duration T = 1/f
H
@ f
H
= 27.64kHz
1
0.9T
s
V
5
Monostable Threshold
5.6
6
6.4
V
t
5
Internal Pulse Width (t
5
= C5 x V
5
/I
5
)
C5 = 220 pF
(see technical note 2)
3.6
s
t
7
Output Pulse Duration (low) - T = 1/f
H
f
H
= 27kHz
f
H
= 70kHz
0.44T
0.41T
0.48T
0.45T
0.52T
0.49T
s
s
V
7
sat
Output Saturation Voltage
I
7
= 600 mA
1.2
2.5
V
t
D
Permissible delay between output pulse
leading edge and flyback pulse leading edge
(for keeping a constant duty cycle) ; T
=
1
f
H
See technical note 4
@ f
H
= 27kHz
0.48 T - t
FLY
s
I
FLY
Flyback Input Current at Pin 8
q
Flyback On
q
Flyback Off
0.7
-1
2
mA
mA
V
8
Clamp voltage at Pin 8
q
I
8 =
1mA
q
I
8
= - 1mA
0.6
- 0.6
V
V
I
8
Current for switching low the output pulse
0.7
2
mA
I
9
Peak control current
0.9
mA
91
02
F
-
0
3
.
T
B
L
TDA9102F
3/7
ELECTRICAL CHARACTERISTICS (continued)
(T
amb
= 25
o
C, V
S
= 12V, refer to the test circuits, unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
HORIZONTAL SECTION
K
9
Phase sensitivity at Pin 9
(See technical note 3)
67.5
degree
V
V
10
Control voltage range
0.5
4.5
V
K
10
Phase control sensitivity at Pin 10
23
26
29
degree
V
HADJ
Horizontal phase adjustment for V
10
varying
from 0.5 to 4.5V (27.64kHz)
Zero degree phase: flyback
centered on the middle of the
pulse at Pin 5
- 45
+ 45
degree
K
1
Phase jitter constant
(
jitter
=
K
1
10
6
.
f
H
)
100
150
ppm
K
2
Frequency drift versus supply voltage
K
2
=
dF
. 10
6
dV . f
H
V
S
= 10.5V to 15.5V
400
ppm
V
VERTICAL SECTION
V
12
Voltage reference at Pin 12
3.2
3.5
3.8
V
I
13
I
12
Current gain at Pin 13
I
12
= 100
A
(I
12
max. = 200
A)
0.94
1
1.06
V
13
Typical Vertical Sawtooth Amplitude
(Pin 13) for Center Frequency
To be adjusted by I
12
4
V
PP
t
FALL
Discharge time at Pin 13
C
18
= 0.22
F, V
13
= 4V
PP
10
22
s
f
VL
Maximum Vertical Frequency
Vertical Sync Low
C
Pin 13
= 220nF, R
Pin 12
= 58k
84
Hz
f
VH
Minimum Vertical Frequency
Vertical Sync High
C
Pin 13
= 220nF, R
Pin 12
= 58k
56
Hz
K
14
Synchro window constant t
s
=
K
14
f
V
(See technical note 6)
0.333
V
14
Sync input threshold (negative edge)
q
Sync high
q
Sync Low
2
8
0.8
V
V
I
14
Current at Pin 14
q
Input high
q
Input Low V
14
= 0.8V
- 10
10
A
A
t
14
Input pulse duration T
=
1
f
V
@ f
V
= 64.75Hz
10
0.5T
s
V
15
Average value of voltage on Pin 15
V
13
= 4V
PP
, V
16
= 2.5V
4
V
II
15
I
Output current at Pin 15
1
mA
K
15
Buffer gain constant at Pin 15
V
15PP
=
K
15
. V
13PP
V
16
= 2.5V
0.95
K
16
Buffer variable gain constant at Pin 15 :
K
16
=
V
15PP
V
16
. V
13
PP
2.5V < V
16
< 4.5V
0.5V < V
16
< 2.5V
0.1
0.1
V
-1
V
-1
I
16
Input bias current at Pin 16
V
16
= 0.5V
- 50
A
I
17
Input bias current at Pin 17
V
17
= 4.5V
50
A
V
18
Average voltage at Pin 18 : V
18
=
2
+
V
18
PP
2
V
17
= 3.5V, R
18
not connected
3
V
K
18
Linearity correction constant : K
18
=
V
18PP
V
17
V
13PP
= 4V,1.5V < V
17
< 4.5V
1
V
19
Voltage reference at Pin 19
(See technical note 5)
7.6
8
8.4
V
I
19
Current at Pin 19
2
mA
91
02
F
-
0
4
.
T
B
L
TDA9102F
4/7
ELECTRICAL CHARACTERISTICS (continued)
(T
amb
= 25
o
C, V
S
= 12V, refer to the test circuits, unless otherwise specified)
Symbol
Parameter
Test conditions
Min.
Typ. Max.
Unit
VERTICAL SECTION
K
17
Frequency drift versus supply voltage K
17
=
dF .
10
6
dV .
f
V
V
S
= 10.5V to 15.5V
300
ppm
V
91
02
F
-
0
5
.
T
B
L
1
2
C2
R1
R2
I1
if
C1
C3
R3
3
HOR. SYNC.
1
HORIZONTAL
OSCILLATOR
V
3L
V
3H
V
3H
V
DC
V
DC
V
3L
91
02
F
-
0
3
.
E
P
S
V (V)
t (s)
V
L
= 5.2V
= 6.8V
V
H
= 6V
V
= 2V
V
LL
1/fv
ts
91
02
F
-
0
4
.
E
P
S
Technical note 1
f
H (nom)
= 26.8 kHz
R1 = 6.8k
R2 = 56 k
C2 = 1.8 nF
f
pull-in
= f
H (nom)
V
3
-
V
1
/ R2
V
1
/ R1
= f
H (nom)
I
f
I
o
(A)
where: V
1
= 3.5V and
V
3
- V
1
is the control
voltage range.
The voltage at Pin 3 is limited by two clamping
diodes at the voltage V
3H
and V
3L
When the PLL1 is synchronized and perfectly
tuned, V
3
= V
1
.
Remark: The value of C2 influences the horizontal
oscillator free running frequency; it doesn't effect
the relative pull-in range. If the horizontal fre-
quency is changed by using R1, the pull-in range
changes accordingly with the formula (A).
Technical note 2
The internal pulse "t
5
", is generated by the current
generator "I
5
" charging the external capacitor
"C5", according with the formula (B):
t
5
=
C5 . V
5
I
5
(
B
)
, t
5
=
T
H
12
is recommended.
Technical note 3
K
9
= 67.5 degrees/volt represents the slope of the
oscillator charging period of the waveform at
Pin 2:
K
9
=
360 x 0.75
4
degree
V
Technical note 4
The second PLL can recover the storage of hori-
zontal output stage maintaining a constant duty
cycle till the trailing edge of the output pulse gets
the trailing edge of the flyback pulse. From this
point on, only the leading edge of the output pulse
will be shifted covering a total phase shift of: 0.30T;
overcoming this value, it will produce a notch in the
output pulse (@ f
H
= 27kHz).
Technical note 5
The voltage reference at Pin 19 can be used to
polarize the DC operating point of the vertical
booster. This voltage corresponds to the double of
the mean value voltage of the vertical sawtooth at
Pin 13.
Technical note 6
V
H
-
V
L
t
s
=
V
H
-
V
LL
1/f
V
t
s
=
(
V
H
-
V
L
)
(
V
H
-
V
LL
)
1
f
V
=
K
14
f
V
TDA9102F
5/7
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