1/20
s
8-bit A/D converter in deep submicron
CMOS technology
s
Single supply voltage: 2.5V
s
Input range: 2Vpp differential
s
40Msps sampling frequency
s
Ultra low power consumption: 40mW @
40MHz (10mW @ 5Msps)
s
ENOB=7.9 @ Nyquist
s
SFDR typically up to 67dB @ Fs=40Msps,
Fin=5MHz
s
Built-in reference voltage with external bias
capability
s
STMicroelectronics 8, 10, 12 and 14-bits ADC
pinout compatibility
DESCRIPTION
The TSA0801 is an 8-bit, 40MHz sampling fre-
quency Analog to Digital converter using a deep
submicron CMOS technology combining high per-
formances and very low power consumption.
The TSA0801 is based on a pipeline structure and
digital error correction to provide excellent static
linearity and go beyond 7.9 effective bits at
Fs=40Msps, and Fin=10MHz.
A voltage reference is integrated in the circuit to
simplify the design and minimize external compo-
nents. It is nevertheless possible to use the circuit
with an external reference.
Differential or single-ended analog inputs can be
applied to the converter. A tri-state capability is
available on the outputs. The output data can be
coded into two different formats. A Data Ready
signal is raised as the data is valid on the output
and can be used for synchronization purposes.
The TSA0801 is available in commercial (0 to
+70
C) and extended (-40 to +85
C) temperature
range, in a small 48 pins TQFP package.
APPLICATIONS
s
Hand-held instrumentation
s
Camcorders
s
Computer scanners
s
Digital communication
ORDER CODE
PIN CONNECTIONS (top view)
PACKAGE
Part Number
Temperature
Range
Package
Conditioning
Marking
TSA080 1CF
0
C to +70
C
TQFP48
Tray
SA0801C
TSA080 1CFT
0
C to +70
C
TQFP48
Tape & Reel
SA0801C
TSA080 1IF
-40
C to +85
C
TQFP48
Tray
SA0801I
TSA080 1IFT
-40
C to +85
C
TQFP48
Tape & Reel
SA0801I
EVAL0801/AA
Evaluation board
7
7 mm TQFP48
VREFM
VREFP
NC
NC
D0(L SB)
D1
D2
D3
D4
VINB
AGND
AGND
index
c orner
13
14 15
16
17
18 1 9 2 0 2 1
22
4 7
1
2
3
4
5
6
7
8
9
10
11
12
23
24
32
31
30
29
28
27
26
25
33
35
34
36
48
44 43
4 2
41
40
39
38 3 7
46
4 5
AGND
VIN
D5
D 6
AVCC
AVCC
AGND
IPOL
INCM
NC
NC
AVCC
DR
NC
OEB
AGND
AVCC
DFSB
VCCB
GNDB
NC
NC
VCCB
GNDB
GNDB
DGND
DVCC
CLK
DGND
VCCB
NC
OR
DGND
DVCC
D7
(MSB)
NC
TSA0801
TSA0801
8-BIT, 40MSPS, 40mW A/D CONVERTER
October 2000
TSA0801
2/20
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
BLOCK DIAGRAM
Symbol
Parameter
Values
Unit
AVCC
Analog Supply voltage
1)
0 to 3.3
V
DVCC
Digital Supply voltage
1)
0 to 3.3
V
VCCB
Digital buffer Supply voltage
1)
0 to 3.3
V
IDout
Digital output current
-100 to 100
mA
Tstg
Storage temperature
+150
C
ESD
Electrical Static Discharge:
- HBM
- CDM-JEDEC Standard
2
1.5
KV
1) All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages
must never exceed -0.3V or VCC+0V
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
AVCC
Analog Supply voltage
2.25
2.5
2.7
V
DVCC
Digital Supply voltage
2.25
2.5
2.7
V
VCCB
Digital buffer Supply voltage
2.25
2.5
2.7
V
VREFP
Forced top voltage reference
1.16
-
AVCC
V
VREFM
Forced bottom reference voltage
0
0
0.5
V
stage
stage
stage
1
2
n
Reference
Timing
circuit
Sequencer-phase shifting
Digital data correction
Buffers
IPOL
VREFM
VREFP
CLK
+2.5V
VIN
VINB
DFSB
OEB
DR
DO
TO
D7
OR
INCM
GND
GNDA
TSA0801
3/20
PIN CONNECTIONS (top view)
PIN DESCRIPTION
VRE FM
VREFP
NC
NC
D0(LS B)
D1
D2
D3
D4
VINB
AGN D
AGND
index
corner
13
14 15
16
17
18
19
20
21
22
47
1
2
3
4
5
6
7
8
9
10
11
12
23
24
32
31
30
29
28
27
26
25
33
35
34
36
48
44
43
42
41
40
39
38
37
46
45
AGND
VIN
D5
D6
AVC C
AVC C
AGND
IPOL
INCM
NC
NC
AVCC
DR
NC
OEB
AGND
AVCC
DFSB
VCCB
GNDB
NC
NC
VCCB
GNDB
GNDB
DGND
DVCC
CLK
DGND
VCCB
NC
OR
DGND
DVCC
D7
(MSB)
NC
TSA0801
Pin No
Name
Description
Observation
Pin No
Name
Descri ption
Observ ation
1
IPOL
Analog bias curr ent input
25
D6
Digital output
CMOS output (2.5V)
2
VREFP
Top voltage reference
1V
26
D5
Digital output
CMOS output (2.5V)
3
VREFM
Bottom vo ltage referen ce
0V
27
D4
Digital output
CMOS output (2.5V)
4
AGND
Analog ground
0V
28
D3
Digital output
CMOS output (2.5V)
5
VIN
Analog input
1Vpp
29
D2
Digital output
CMOS output (2.5V)
6
AGND
Analog ground
0V
30
D1
Digital output
CMOS output (2.5V)
7
VINB
Inverted analog input
1Vpp
31
D0(LSB)
Digital output
CMOS output (2.5V)
8
AGND
Analog ground
0V
32
NC
Non conne cted
9
INCM
Input common mode
0.5V
33
NC
Non conne cted
10
AGND
Analog ground
0V
34
NC
Non conne cted
11
AVCC
Analog power supply
2.5V
35
NC
Non conne cted
12
AVCC
Analog power supply
2.5V
36
NC
Non conne cted
13
DVCC
Digital power supply
2.5V
37
NC
Non conne cted
14
DVCC
Digital power supply
2.5V
38
DR
Data Ready output
CMOS output (2.5V)
15
DGND
Digital ground
0V
39
VCCB
Digital Buffer power supply
2. 5V
16
CLK
Clock input
2.5V compati ble CMOS input
40
GNDB
Digital Buffer ground
0V
17
DGND
Digital ground
0V
41
VCCB
Digital Buffer power supply
2. 5V
18
NC
Non connected
42
NC
Non conne cted
19
DGND
Digital ground
0V
43
NC
Non conne cted
20
GNDB
Digital buffer gro und
0V
44
OEB
Output Enable input
2. 5V compatib le CMOS input
21
GNDB
Digital buffer ground
0V
45
DFSB
Data Format Select input
2. 5V compatib le CMOS input
22
VCCB
Digital buffer power supply
2.5V
46
AVCC
Analog power supply
2. 5V
23
OR
Out Of Range output
CMOS outp ut (2.5V)
47
AVCC
Analog power supply
2. 5V
24
D7(MSB)
Most Significa nt Bit output
CMOS outp ut (2.5V)
48
AGND
Analog ground
0V
TSA0801
4/20
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin=1MHz, Vin@ -1.0dBFS, VREFM = 0V
Tamb = 25
C (unless otherwise specified)
TIMING CHARACTERISTICS
TIMING DIAGRAM
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
FS
Sampling Frequency
0.5
40
MHz
DC
Clock Duty Cycle
45
50
55
%
TC1
Clock pulse width (high)
11
12.5
ns
TC2
Clock pulse width (low)
11
12.5
ns
Tod
Data Output Delay (Fall of Clock
to Data Valid)
10pF load capacitance
5
ns
Tpd
Data Pipeline delay
6.5
cycles
Ton
Falling edge of OEB to digital
output valid data
1
ns
Toff
Rising edge of OEB to digital
output tri-state
1
ns
N-1
N
N+1
N+6
N+7
N+2
N+5
N+3
N+4
N+8
N
N+1
N-2
N-3
N-4
N-5
N-6
N-7
N-8
CLK
DR
Tod
Ton
Toff
6.5 clk cycles
HZ state
DATA
OUT
OEB
TSA0801
5/20
CONDITIONS
AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V
Tamb = 25
C (unless otherwise specified)
ANALOG INPUTS
REFERENCE VOLTAGE
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
VIN-VINB Full scale reference voltage
2.0
Vpp
Cin
Input capacitance
7.0
pF
BW
Analog Input Bandwitdh
Vin@-1dBFS, FS=40Msps
100
MHz
ERB
Effective Resolution Bandwidth
1)
60
MHz
1) See parameters definition for more information
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
VREFP
Top internal reference voltage
0.89
1.03
1.16
V
Tmin= -40
C to Tmax= 85
C
1)
0.88
1.16
V
Vpol
Analog bias voltage
1.19
1.27
1.35
V
Tmin= -40
C to Tmax= 85
C
1)
1.18
1.36
V
Ipol
Analog bias current
Normal operating mode
50
70
100
A
Ipol
Analog bias current
Shutdown mode
0
A
VINCM
Input common mode voltage
0.46
0.57
0.66
V
Tmin= -40
C to Tmax= 85
C
1)
0.46
0.66
V
1) Not fully tested over the temperature range. Guaranted by sampling.
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