1/19
s
10-bit A/D converter in deep submicron
CMOS technology
s
Single supply voltage: 2.5V
s
Input range: 2Vpp differential
s
50Msps sampling frequency
s
Ultra low power consumption: 50mW @
50Msps
s
ENOB=9.4 @ Fs=50Msps, Fin=15MHz
s
SFDR typically up to 72dB @ Fs=50Msps,
Fin=5MHz
s
Built-in reference voltage with external bias
capability
s
STMicroelectronics 8, 10, 12 and 14-bits ADC
pinout compatibility
DESCRIPTION
The TSA1002 is a 10-bit, 50Msps sampling
frequency Analog to Digital converter using a
CMOS technology combining high performances
and very low power consumption.
The TSA1002 is based on a pipeline structure and
digital error correction to provide excellent static
linearity and guarantee 9.4 effective bits at
Fs=50Msps, and Fin=15MHz.
A voltage reference is integrated in the circuit to
simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with an external reference.
Especially designed for high speed, low power
applications, the TSA1002 only dissipates 50mW
at 50Msps. A tri-state capability, available on the
output buffers, enables to address several slave
ADCs by a unique master.
The output data can be coded into two different
formats. A Data Ready signal is raised as the data
is valid on the output and can be used for
synchronization purposes.
The TSA1002 is available in commercial (0 to
+70C) and extended (-40 to +85C) temperature
range, in a small 48 pins TQFP package.
APPLICATIONS
s
Medical imaging and ultrasound
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Portable instrumentation
s
Cable Modem Receivers
s
High resolution fax and scanners
s
High speed DSP interface
ORDER CODE
PIN CONNECTIONS (top view)
PACKAGE
Part Number
Temperature
Range
Package
Conditioning
Marking
TSA1002CF
0C to +70C
TQFP48
Tray
SA1002C
TSA1002CFT
0C to +70C
TQFP48
Tape & Reel
SA1002C
TSA1002IF
-40C to +85C
TQFP48
Tray
SA1002I
TSA1002IFT
-40C to +85C
TQFP48
Tape & Reel
SA1002I
EVAL1002/AA
Evaluation board
7
7 mm
TQFP48
VREFM
VREFP
D0 (LSB)
D1
D2
D3
D4
D5
D6
VINB
AGND
AGND
index
corner
13
14 15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
23
24
32
31
30
29
28
27
26
25
33
35
34
36
47
48
44 43
42
41
40
39
38
37
46
45
AGND
VIN
D7
D8
AVCC
AVCC
AGND
IPOL
INCM
NC
NC
AVCC
DR
NC
OE
B
AGND
AVCC
D
FSB
VCC
B
GNDB
NC
NC
VCCB
GN
DB
GND
B
DGND
DVC
C
CL
K
DGN
D
VC
CB
NC
OR
DGN
D
DV
CC
D9 (
M
SB)
NC
TSA1002
TSA1002
10-BIT, 50MSPS, 50mW A/D CONVERTER
October 2000
TSA1002
2/19
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
BLOCK DIAGRAM
Symbol
Parameter
Values
Unit
AVCC
Analog Supply voltage
1)
0 to 3.3
V
DVCC
Digital Supply voltage
1)
0 to 3.3
V
VCCB
Digital buffer Supply voltage
1)
0 to 3.3
V
IDout
Digital output current
-100 to 100
mA
Tstg
Storage temperature
+150
C
ESD
Electrical Static Discharge
- HBM
- CDM-JEDEC Standard
2
1.5
KV
1) All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages
must never exceed -0.3V or VCC+0V
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
AVCC
Analog Supply voltage
2.25
2.5
2.7
V
DVCC
Digital Supply voltage
2.25
2.5
2.7
V
VCCB
Digital buffer Supply voltage
2.25
2.5
2.7
V
VREFP
Forced top reference voltage
1.16
-
AVCC
V
VREFM
Forced bottom reference voltage
0
0
0.5
stage
stage
stage
1
2
n
Reference
Timing
circuit
Sequencer-phase shifting
Digital data correction
Buffers
IPOL
VREFM
VREFP
CLK
+2.5V
VIN
VINB
DFSB
OEB
DR
DO
TO
D9
OR
INCM
GND
GNDA
TSA1002
3/19
PIN CONNECTIONS (top view)
PIN DESCRIPTION
VREFM
VREFP
D0 (LSB)
D1
D2
D3
D4
D5
D6
VINB
AGND
AGND
index
corner
13
14 15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
23
24
32
31
30
29
28
27
26
25
33
35
34
36
47
48
44
43
42
41
40
39
38
37
46
45
AGND
VIN
D7
D8
AVCC
AVCC
AGND
IPOL
INCM
NC
NC
AVC
C
DR
NC
OE
B
AG
N
D
AVC
C
DF
S
B
V
CCB
G
NDB
NC
NC
V
CCB
GN
D
B
GN
D
B
DG
ND
DV
C
C
CL
K
DG
ND
VC
C
B
NC
OR
DG
ND
DV
C
C
D
9
(MSB)
NC
TSA1002
Pin No
Name
Description
Observation
Pin No
Name
Description
Observation
1
IPOL
Analog bias current input
25
D8
Digital output
CMOS output (2.5V)
2
VREFP
Top voltage reference
1V
26
D7
Digital output
CMOS output (2.5V)
3
VREFM
Bottom voltage reference
0V
27
D6
Digital output
CMOS output (2.5V)
4
AGND
Analog ground
0V
28
D5
Digital output
CMOS output (2.5V)
5
VIN
Analog input
1Vpp
29
D4
Digital output
CMOS output (2.5V)
6
AGND
Analog ground
0V
30
D3
Digital output
CMOS output (2.5V)
7
VINB
Inverted analog input
1Vpp
31
D2
Digital output
CMOS output (2.5V)
8
AGND
Analog ground
0V
32
D1
Digital output
CMOS output (2.5V)
9
INCM
Input common mode
0.5V
33
D0(LSB)
Least Significant Bit output
CMOS output (2.5V)
10
AGND
Analog ground
0V
34
NC
Non connected
11
AVCC
Analog power supply
2.5V
35
NC
Non connected
12
AVCC
Analog power supply
2.5V
36
NC
Non connected
13
DVCC
Digital power supply
2.5V
37
NC
Non connected
14
DVCC
Digital power supply
2.5V
38
DR
Data Ready output
CMOS output (2.5V)
15
DGND
Digital ground
0V
39
VCCB
Digital Buffer power supply
2.5V
16
CLK
Clock input
2.5V compatible CMOS input
40
GNDB
Digital Buffer ground
0V
17
DGND
Digital ground
0V
41
VCCB
Digital Buffer power supply
2.5V
18
NC
Non connected
42
NC
Non connected
19
DGND
Digital ground
0V
43
NC
Non connected
20
GNDB
Digital buffer ground
0V
44
OEB
Output Enable input
2.5V compatible CMOS input
21
GNDB
Digital buffer ground
0V
45
DFSB
Data Format Select input
2.5V compatible CMOS input
22
VCCB
Digital buffer power supply
2.5V
46
AVCC
Analog power supply
2.5V
23
OR
Out Of Range output
CMOS output (2.5V)
47
AVCC
Analog power supply
2.5V
24
D9(MSB)
Most Significant Bit output
CMOS output (2.5V)
48
AGND
Analog ground
0V
TSA1002
4/19
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V
Tamb = 25C (unless otherwise specified)
TIMING CHARACTERISTICS
TIMING DIAGRAM
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
FS
Sampling Frequency
0.5
50
Msps
DC
Clock Duty Cycle
45
50
55
%
TC1
Clock pulse width (high)
9
10
ns
TC2
Clock pulse width (low)
9
10
ns
Tod
Data Output Delay (Fall of Clock
to Data Valid)
10pF load capacitance
5
ns
Tpd
Data Pipeline delay
6.5
cycles
Ton
Falling edge of OEB to digital
output valid data
1
ns
Toff
Rising edge of OEB to digital
output tri-state
1
ns
N-1
N
N+1
N+6
N+7
N+2
N+5
N+3
N+4
N+8
N
N+1
N-2
N-3
N-4
N-5
N-6
N-7
N-8
CLK
DR
Tod
Ton
Toff
6.5 clk cycles
HZ state
DATA
OUT
OEB
TSA1002
5/19
CONDITIONS
AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps,Fin= 1MHz, Vin@ -1.0dBFS, VREFM= 0V
Tamb = 25C (unless otherwise specified)
ANALOG INPUTS
REFERENCE VOLTAGE
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
VIN-VINB Full scale reference voltage
2.0
Vpp
Cin
Input capacitance
7.0
pF
BW
Analog Input Bandwidth
Vin@ Full scale, FS=50Msps
100
MHz
ERB
Effective Resolution Bandwidth
1)
1) See parameters definition for more information
60
MHz
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
VREFP
Top internal reference voltage
0.91
1.03
1.14
V
Tmin= -40C to Tmax= 85C
1)
0.88
1.16
V
Vpol
Analog bias voltage
1.20
1.27
1.35
V
Tmin= -40C to Tmax= 85C
1)
1.18
1.36
V
Ipol
Analog bias current
Normal operating mode
50
70
100
A
Ipol
Analog bias current
Shutdown mode
0
A
VINCM
Input common mode voltage
0.47
0.57
0.68
V
Tmin= -40C to Tmax= 85C
1)
0.46
0.66
V
1) Not fully tested over the temperature range. Guaranted by sampling.
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