VIPer100/SP

VIPer100A/ASP

SMPS PRIMARY I.C.

May 1999

BLOCK DIAGRAM

T YPE

DSS

DS(on)

VIPer100/SP

620V

3 A

2.5

VIPer100A/ASP

700V

3 A

2.8

FEATURE

ADJUSTABLE SWITCHING FREQUENCY UP
TO 200KHZ

CURRENT MODE CONTROL

SOFT START AND SHUT DOWN CONTROL

AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
"BLUE ANGEL" NORM (<1W TOTAL POWER
CONSUMPTION)

INTERNALLY TRIMMED ZENER
REFERENCE

UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS

INTEGRATED START-UP SUPPLY

AVALANCHE RUGGED

OVERTEMPERATURE PROTECTION

LOW STAND-BY CURRENT

ADJUSTABLE CURRENT LIMITATION

DESCRIPTION
VIPer100

/100A,

made

using

VIPower M0

Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (620V or 700V / 3A).
Typical applications cover off line power supplies
with a secondary power capability of 50W in wide
range condition and 100W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50%

less

components when

compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode without extra components.

PowerSO-10

PENTAWATT HV

(022Y)

OSC

COMP

DRAIN

SOURCE

13 V

UVLO

LOGIC

SECURITY

LATCH

PWM

LATCH

R/S

R2 R3

OSCILLATOR

OVERTEMP.

DETECTOR

ERROR

AMPLIFIER

0.5 V

+
_

1.7

DELAY

25 0 ns

BLANKING

CURRENT

AMPLIFIER

ON/OFF

0.5V

1 V/A

4.5 V

1/20

ABSOLUTE MAXIMUM RATING

Symb ol

Parameter

Value

Uni t

Continuous Drain-Source Voltage (Tj = 25 to 125

for VIPer100/ SP
for VIPer100A/ASP

-0.3 to 620
-0.3 to 700

V
V

Maximum Current

I nternally Limited

Supply Voltage

0 t o 15

OSC

Voltage Range Input

0 t o V

COMP

Voltage Range Input

0 to 5

COMP

Maximum Cont inuous Current

esd

Electrostatic discharge (R = 1. 5 K

C = 100pF)

4000

D(AR)

Avalanche Drain-Source Current, Repetit ive or Not-Repet itive
(T

= 100

C, Pulse Width Limited by T

max,

<1%)

for VIPer100/ SP
for VIPer100A/ASP

1.4

A
A

tot

Power Dissipation at T c = 25

Junct ion Operating Temperature

I nternally Limited

s tg

St orage Temperature

-65 t o 150

THERMAL DATA

PENT AW ATT-HV

Po werSO-10(*)

t hj-ca se

Thermal Resistance Junction-case

Max

1.4

C/W

th j-a mb.

Thermal Resistance Ambient -case

Max

C/W

(*) When mounted using the minimum recommended pad size on FR-4 board.

CURRENT AND VOLTAGE CONVENTIONS

13V

OSC

COMP SOURCE

DRAIN

VDD

COMP

OSC

COMP

OSC

FC00020

CONNECTION DIAGRAMS (Top View)

PENTAWATT HV

PENTAWATT HV (022Y)

PowerSO-10

VIPer100/SP - VIPer100A/ASP

2/20

PINS FUNCTIONAL DESCRIPTION

DRAIN PIN:
Integrated power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation. The device
is able to handle an unclamped current during its
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.

SOURCE PIN:
Power MOSFET source pin. Primary side circuit
common ground connection.

VDD PIN :
This pin provides two functions :

It corresponds to the low voltage supply of the
control part of the circuit. If V

goes below 8V,

the start-up current source is activated and the
output power MOSFET is switched off until the
V

voltage reaches 11V. During this phase,

the internal current consumption is reduced,
the V

pin is sourcing a current of about 2mA

and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
device tries to start up by switching again.

This pin is also connected to the error
amplifier, in order to allow primary as well as
secondary regulation configurations. In case of
primary regulation, an internal 13V trimmed
reference voltage is used to maintain V

13V. For secondary regulation, a voltage
between 8.5V and 12.5V will be put on V

by transformer design, in order to stuck the
output of the transconductance amplifier to the
high state. The COMP pin behaves as a

constant current source, and can easily be
connected to the output of an optocoupler.
Note that any overvoltage due to regulation
loop failure is still detected by the error
amplifier through the V

voltage, which

cannot overpass 13V. The output voltage will
be somewhat higher than the nominal one, but
still under control.

COMP PIN :
This pin provides two functions :

It is the output of the error transconductance
amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the
needed value with usual components value. As
stated

above,

secondary

regulation

configurations are also implemented through
the COMP pin.

When the COMP voltage is going below 0.5V,
the shut-down of the circuit occurs, with a zero
duty cycle for the power MOSFET. This feature
can be used to switch off the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or open load condition.

OSC PIN :
An R

-C

network must be connected on that pin

to define the switching frequency. Note that
despite the

connection of R

to V

, no

significant frequency change occurs for V

varying from 8V to 15V. It provides also a
synchronisation capability, when connected to an
external frequency source.

ORDERING NUMBERS

PENT AW ATT HV

PENTAW AT T HV (022Y)

Pow erSO-10

VI Per100

VIPer100A

VIPer100 (022Y)

VI Per100A (022Y)

VIPer100SP

VIPer100ASP

VIPer100/SP - VIPer100A/ASP

3/20

AVALANCHE CHARACTERISTICS

Symb ol

Parameter

Max Valu e

Uni t

D(a r)

Avalanche Current , Repet itive or Not -Repetitive
(pulse widt h limited by T

max,

< 1%)

for VIPer100/ SP
for VIPer100A/ASP

(see fig. 12)

1.4

A
A

(ar)

Single Pulse Avalanche Energy
(starting T

= 25

C, I

= I

D( ar)

)

(see fig.12)

ELECTRICAL CHARACTERISTICS (T

= 25

C, V

= 13 V, unless otherwise specified)

POWER SECTION

Symb ol

Parameter

T est Con ditio ns

Mi n.

Typ .

Max.

Un it

DSS

Drain-Source Voltage

= 1 mA

COM P

= 0 V

for VIPer100/SP
for VIPer100A/ ASP

(see f ig. 5)

620
700

V
V

DSS

Of f-St ate Drain Current

CO MP

= 0 V

= 125

= 620 V

for VIPer100/ SP

= 700 V

for VIPer100A/ASP

1
1

mA
mA

DS( on)

St atic Drain Source on
Resistance

= 2 A

for VIPer100/SP
for VIPer100A/ ASP
I

= 2 A

= 100

for VIPer100/SP
for VIPer100A/ ASP

2.0
2.3

2.5
2.8

4.5
5.0

Fall T ime

ID = 0.2 A V

= 300 V (1)

(see fig. 3)

100

Rise Time

= 2 A

i n

= 300 V (1)

(see fig. 3)

OSS

Output Capacit ance

= 25 V

150

(1) On Inductive Load, Clamped.

SUPPLY SECTION

Symb ol

Parameter

T est Con ditio ns

Mi n.

Typ .

Max.

Un it

DDch

St art-up Charging
Current

= 5 V

= 70 V

(see fig. 2 and fig. 15)

-2

DD0

Operating Supply Current V

= 12 V,

= 0 KHz

(see fig. 2)

DD1

Operating Supply Current V

= 12 V,

= 100 KHz

15. 5

DD2

Operating Supply Current V

= 12 V,

= 200 KHz

DDo ff

Undervoltage Shut down

(see fig. 2)

DDo n

Undervoltage Reset

(see fig. 2)

DDhyst

Hysteresis St art -up

(see fig. 2)

2. 4

VIPer100/SP - VIPer100A/ASP

4/20

ELECTRICAL CHARACTERISTICS (continued)

OSCILLATOR SECTION

Symb ol

Parameter

T est Con ditio ns

Mi n.

Typ .

Max.

Un it

Oscillator F requency
Total Variation

= 8.2 K

=2.4 nF

= 9 to15 V

with R

(see fig. 6 and fig. 9)

100

110

KHz

OSCih

Oscillator Peak Volt age

7.1

OSCi l

Oscillator Valley Voltage

3.7

ERROR AMPLIFIER SECTION

Symb ol

Parameter

Test Cond ition s

Mi n.

Typ .

Max.

Un it

DDreg

Regulation Point

COM P

= 0 mA

(see f ig.1)

12. 6

13.4

DDreg

Total Variation

= 0 to 100

Unity Gain Bandwidt h

From Input = V

t o O utput = V

COM P

CO MP pin is open (see fig. 10)

150

KHz

VOL

Open Loop Voltage
Gain

CO MP pin is open (see fig. 10)

DC T ransconduct ance

COMP

= 2.5 V

(see fig. 1)

1. 1

1.5

1.9

mA/V

COMPL O

Output Low Level

COM P

= -400

= 14 V

0.2

COMPHI

Output High Level

COM P

= 400

= 12 V

4.5

COM PLO

Output Low Current
Capability

COMP

= 2.5 V

= 14 V

-600

COMPHI

Output High Current
Capability

COMP

= 2.5 V

= 12 V

600

PWM COMPARATOR SECTION

Symb ol

Parameter

Test Cond ition s

Mi n.

Typ .

Max.

Un it

COMP

Dpea k

COMP

= 1 to 3 V

0. 7

1.3

V/A

COMPof f

COMP

off set

Dp eak

= 10 mA

0.5

Dpeak

Peak Current Limitat ion V

= 12 V

COMP pin open

5.3

Current Sense Delay
to turn-off

= 1 A

250

Blanking Time

250

360

on( mi n)

Minimum on T ime

350

SHUTDOWN AND OVERTEMPERATURE SECTION

Symb ol

Parameter

Test Cond ition s

Mi n.

Typ .

Max.

Un it

COMPth

Restart threshold

(see f ig. 4)

0.5

DI Ssu

Disable Set Up Time

(see f ig. 4)

1.7

t sd

Thermal Shutdown
Temperat ure

(see f ig. 8)

140

170

hyst

Thermal Shutdown
Hysteresis

(see f ig. 8)

VIPer100/SP - VIPer100A/ASP

5/20

OPERATION DESCRIPTION :

CURRENT MODE TOPOLOGY:
The current mode control method, like the one
integrated in the VIPer100/100A uses two control
loops - an inner current control loop and an outer
loop

for voltage control. When the Power

MOSFET output transistor is on, the inductor
current (primary side of the transformer) is
monitored with a SenseFET technique and
converted into a voltage V

proportional to this

current. When V

reaches V

COMP

(the amplified

output voltage error) the power switch is switched
off. Thus, the outer voltage control loop defines
the level at which the inner loop regulates peak
current through the power switch and the primary
winding of the transformer.
Excellent open loop D.C. and dynamic line
regulation is ensured due to the inherent input
voltage feedforward characteristic of the current
mode control. This results in an improved line
regulation,

instantaneous

correction

line

changes and better stability for the voltage
regulation loop.
Current mode topology also ensures good
limitation in the case of short circuit. During a first
phase

the

output

current

increases

slowly

following the dynamic of the regulation loop. Then
it

reaches

the

maximum

limitation

current

internally set and finally stops because the power
supply on V

is no longer correct. For specific

applications the maximum peak current internally
set can be overridden by externally limiting the
voltage

excursion

the

COMP

pin.

integrated

blanking

filter

inhibits

the

PWM

comparator output for a short time after the
integrated Power MOSFET is switched on. This
function

prevents

anomalous

premature

termination of the switching pulse in the case of
current

spikes

caused

primary

side

capacitance or secondary side rectifier reverse
recovery time.

STAND-BY MODE
Stand-by operation in nearly open load condition
automatically leads to a burst mode operation
allowing voltage regulation on the secondary
side. The transition from normal operation to
burst mode operation happens for a power P

STBY

given by :

STBY

1
2

STBY

Where:
L

is the primary inductance of the transformer.

is the normal switching frequency.

STBY

the

minimum

controllable

current,

corresponding to the minimum on time that the
device is able to provide in normal operation. This
current can be computed as :

STBY

(

)

+ t

is the sum of the blanking time and of the

propagation time of the internal current sense
and comparator, and represents roughly the
minimum on time of the device. Note that P

STBY

may be affected by the efficiency of the converter
at low load, and must include the power drawn on
the primary auxiliary voltage.
As soon as the power goes below this limit, the
auxiliary secondary voltage starts to increase
above the 13V regulation level forcing the output
voltage of the transconductance amplifier to low
state (V

COMP

< V

COMPth

). This situation leads to

the shutdown mode where the power switch is
maintained in the off state, resulting in missing
cycles and zero duty cycle. As soon as V

gets

back to the regulation level and the V

COMPth

threshold is reached, the device operates again.
The above cycle repeats indefinitely, providing a
burst mode of which the effective duty cycle is
much lower than the minimum one when in
normal

operation.

The

equivalent switching

frequency is also lower than the normal one,
leading to a reduced consumption on the input
mains lines. This mode of operation allows the
VIPer100/100A to meet the new German "Blue
Angel" Norm with less than 1W total power
consumption for the system when working in
stand-by. The output voltage remains regulated
around the normal level, with a low frequency
ripple corresponding to the burst mode. The
amplitude of this ripple is low, because of the
output capacitors and of the low output current
drawn in such conditions.The normal operation
resumes automatically when the power get back
to higher levels than P

STBY

HIGH

VOLTAGE

START-UP

CURRENT

SOURCE
An

integrated high

voltage

current

source

provides a bias current from the DRAIN pin
during the start-up phase. This current is partially
absorbed by internal control circuits which are

VIPer100/SP - VIPer100A/ASP

12/20

placed into a standby mode with reduced
consumption and also provided to the external
capacitor connected to the V

pin. As soon as

the voltage on this pin reaches the high voltage
threshold V

DDon

of the UVLO logic, the device

turns into active mode and starts switching. The
start up current generator is switched off, and the
converter should normally provide the needed
current on the V

pin through the auxiliary

winding of the transformer, as shown on figure
15.
In case of abnormal condition where the auxiliary
winding is unable to provide the low voltage
supply current to the V

pin (i.e. short circuit on

the

output

the

converter), the

external

capacitor discharges itself down to the low
threshold voltage V

DDoff

of the UVLO logic, and

the device get back to the inactive state where
the internal circuits are in standby mode and the
start up current source is activated. The converter
enters a endless start up cycle, with a start-up
duty cycle defined by the ratio of charging current
towards discharging when the VIPer100/100A
tries to start. This ratio is fixed by design to 2 to
15, which gives a 12% start up duty cycle while
the power dissipation at start up is approximately
0.6 W, for a 230 Vrms input voltage. This low
value of start-up duty cycle prevents the stress of
the output rectifiers and of the transformer when

in short circuit.
The external capacitor C

VDD

on the V

pin must

be sized according to the time needed by the
converter to start up, when the device starts
switching. This time t

depends on many

parameters, among which transformer design,
output

capacitors,

soft

start

feature

and

compensation network

implemented

the

COMP pin. The following formula can be used for
defining the minimum capacitor needed:

VDD

DDhyst

where:

is the consumption current on the V

when switching. Refer to specified I

DD1

and I

DD2

values.
t

is the start up time of the converter when the

device begins to switch. Worst case is generally
at full load.
V

DDhyst

is the voltage hysteresis of the UVLO

logic. Refer to the minimum specified value.
Soft start feature can be implemented on the
COMP pin through a simple capacitor which will
be also used as the compensation network. In
this case, the regulation loop bandwidth is rather
low, because of the large value of this capacitor.
In case a large regulation loop bandwidth is
mandatory, the schematics of figure 16 can be

Figure 15: Behaviour of the high voltage current source at start-up

Ref.

UNDERVOLTAGE
LOCK OUT LOGIC

15 mA

1 mA

3 mA

2 mA

15 mA

VDD

DRAIN

SOURCE

VIPer100

Auxiliary primary

winding

VDD

VDDoff

VDDon

Start up duty cycle ~ 12%

VDD

FC0010 0

VIPer100/SP - VIPer100A/ASP

13/20

used. It mixes a high performance compensation
network together with a separate high value soft
start capacitor. Both soft start time and regulation
loop bandwidth can be adjusted separately.
If the device is intentionally shut down by putting
the COMP pin to ground, the device is also
performing start-up cycles, and the V

voltage is

oscillating between V

DDon

and V

DDoff

. This voltage

can be used for supplying external functions,
provided that their consumption doesn't exceed
0.5mA. Figure 17 shows a typical application of
this function, with a latched shut down. Once the
"Shutdown" signal has been activated, the device
remains in the off state until the input voltage is
removed.

TRANSCONDUCTANCE ERROR AMPLIFIER
The VIPer100/100A includes a transconductance
error amplifier. Transconductance Gm is the
change in output current (I

COMP

) versus change

in input voltage (V

). Thus:

COMP

The output impedance Z

COMP

at the output of this

amplifier (COMP pin) can be defined as:

COMP

This last equation shows that the open loop gain
A

VOL

can be related to G

and Z

COMP

VOL

= G

x Z

COMP

where G

value for VIPer100/100A is 1.5 mA/V

typically.
G

is well defined by specification, but Z

COMP

and

therefore

VOL

are

subject

large

tolerances. An impedance Z can be connected
between the COMP pin and ground in order to
define more accurately the transfer function F of
the error amplifier, according to the following
equation, very similar to the one above:
F

(S)

= Gm x Z(S)

The

error

amplifier

frequency

response

reported in figure 10 for different values of a
simple resistance connected on the COMP pin.
The unloaded transconductance error amplifier
shows an internal Z

COMP

of about 330 K

. More

complex impedance can be connected on the
COMP pin to achieve different compensation
laws. A capacitor will provide an integrator
function, thus eliminating the DC static error, and
a resistance in series leads to a flat gain at higher
frequency, insuring a correct phase margin. This
configuration is illustrated on figure 18.
As shown in figure 18 an additional noise filtering
capacitor of 2.2 nF is generally needed to avoid
any high frequency interference.
It can be also interesting to implement a slope
compensation when working in continuous mode
with duty cycle higher than 50%. Figure 19 shows
such a configuration. Note that R1 and C2 build
the classical compensation network, and Q1 is
injecting the slope compensation with the correct
polarity from the oscillator sawtooth.

EXTERNAL CLOCK SYNCHRONIZATION:
The

OSC

provides

synchronisation

capability,

when

connected to

external

frequency source. Figure 20 shows one possible

Figure 17: Latched Shut Down

13V

OSC

COMP SOURCE

DRAIN

VDD

VIPER100

Shutdown

FC00110

Figure 16: Mixed Soft Start and Compensation

AUXIL IARY
WINDING

13V

OSC

COMP

SOURCE

DRAIN

VDD

U1
VIPER 100

+ C2

+ C3

FC00131

VIPer100/SP - VIPer100A/ASP

14/20

schematic to be adapted depending the specific
needs. If the proposed schematic is used, the
pulse duration must be kept at a low value (500ns
is sufficient) for minimizing consumption. The
optocoupler must be able to provide 20mA
through the optotransistor.

PRIMARY PEAK CURRENT LIMITATION
The primary I

DPEA K

current and, as resulting

effect, the output power can be limited using the
simple circuit shown in figure 21. The circuit
based on Q1, R

and R

clamps the voltage on

the COMP pin in order to limit the primary peak
current of the device to a value:

DPEAK

COMP

0.5

where:

COMP

0.6

The suggested value for R

is in the range of

220K

OVER-TEMPERATURE PROTECTION:

Over-temperature protection is based on chip
temperature sensing. The minimum junction
temperature at which over-temperature cut-out
occurs is 140

C while the typical value is 170

The device is automatically restarted when the
junction temperature decreases to the restart
temperature threshold that is typically 40

C below

the shutdown value (see figure 8).

Figure 19: Slope Compensation

FC00141

13V

OSC

COMP

SOURCE

DRAIN

VDD

VIPER100

13V

OSC

COMP

SOURCE

DRAIN

VDD

VIPER100

FC00121

Figure 18: Typical Compensation Network

13V

OSC

COMP SOURCE

DRAIN

VDD

U1
VIPER100

10 k

FC00220

Figure 20:External Clock Synchronization

Figure 21:Current Limitation Circuit Example

13V

OSC

COMP

SOURCE

DRAIN

VDD

VIPER100

FC00240

VIPer100/SP - VIPer100A/ASP

15/20

VIPerXX0

13V

OSC

COMP

SOURCE

DRAIN

VDD

ISO1

From input

d iode s bridge

To sec ond a ry

filtering a nd load

FC00500

Figure 22: Recommended layout

LAYOUT CONSIDERATIONS
Some simple rules insure a correct running of
switching power supplies. They may be classified
into two categories:

To minimise power loops: the way the switched
power current must be carefully analysed and
the corresponding paths must present the
smallest inner loop area as possible. This
avoids radiated EMC noises, conducted EMC
noises by magnetic coupling, and provides a
better

efficiency

eliminating

parasitic

inductances, especially on secondary side.

To use different tracks for low level signals and

power ones. The interferences due to a mixing
of signal and power may result in instabilities
and/or anomalous behaviour of the device in
case

violent

power

surge

(Input

overvoltages, output short circuits...).

In case of VIPer, these rules apply as shown on
figure 22.

The loops C1-T1-U1, C5-D2-T1,

C7-D1-T1 must be minimised. C6 must be as
close

possible

from

T1.

The

signal

components C2, ISO1, C3 and C4 are using a
dedicated track to be connected directly to the
source of the device.

VIPer100/SP - VIPer100A/ASP

16/20

DIM.

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

4.30

4.80

0.169

0.189

1.17

1.37

0.046

0.054

2.40

2.80

0.094

0.110

0.35

0.55

0.014

0.022

0.60

0.80

0.024

0.031

4.90

5.28

0.193

0.208

7.42

7.82

0.292

0.308

9.30

9.70

0.366

0.382

10.40

0.409

10.05

10.40

0.396

0.409

16.60

17.30

0.653

0.681

14.60

15.22

0.575

0.599

21.20

21.85

0.835

0.860

22.20

22.82

0.874

0.898

2.60

3.00

0.102

0.118

15.10

15.80

0.594

0.622

6.00

6.60

0.236

0.260

2.50

3.10

0.098

0.122

7.56

8.16

0.298

0.321

0.50

0.020

Diam.

3.70

3.90

0.146

0.154

Diam

Resin

between

leads

P023H3

PENTAWATT HV (VERTICAL) MECHANICAL DATA

VIPer100/SP - VIPer100A/ASP

17/20

DIM.

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

4.30

4.80

0.169

0.189

1.17

1.37

0.046

0.054

2.40

2.80

0.094

0.110

0.35

0.55

0.014

0.022

0.60

0.80

0.024

0.031

4.90

5.28

0.193

0.208

7.42

7.82

0.292

0.308

9.30

9.70

0.366

0.382

10.40

0.409

10.05

10.40

0.396

0.409

16.42

17.42

0.646

0.686

14.60

15.22

0.575

0.599

20.52

21.52

0.808

0.847

2.60

3.00

0.102

0.118

15.10

15.80

0.594

0.622

6.00

6.60

0.236

0.260

2.50

3.10

0.098

0.122

5.00

5.70

0.197

0.224

0.50

0.020

Diam.

3.70

3.90

0.146

0.154

Diam

Resin

between

leads

P023H2

PENTAWATT HV 022Y(VERTICAL HIGH PITCH) MECHANICAL DATA

VIPer100/SP - VIPer100A/ASP

18/20

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

http://www.st.com

VIPer100/SP - VIPer100A/ASP

20/20

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: VIPer100A

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: VIPer100A