VIPer20B
VIPer20BSP
SMPS PRIMARY I.C.
PRELIMINARY DATA
September 1999
BLOCK DIAGRAM
VDD
OSC
COMP
DRAIN
SOURCE
13 V
UVLO
LOGIC
SECURITY
LATCH
PWM
LATCH
FF
FF
R/S
S
Q
S
R1
R2 R3
Q
OSCILLATOR
OVERTEMP.
DETECTOR
ERROR
AMPLIFIER
_
+
0.5 V
+
_
2
s
delay
300 ns
Blanking
CURRENT
AMPLIFIER
ON/OFF
0.5V
6 V/A
_
+
+
_
4.5 V
FC00490
T YPE
V
DSS
I
n
R
DS(on)
VIPer20B/ SP
400V
1.3 A
8.7
FEATURE
s
ADJUSTABLE SWITCHING FREQUENCY UP
TO 200KHZ
s
CURRENT MODE CONTROL
s
SOFT START AND SHUT DOWN CONTROL
s
AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
"BLUE ANGEL" NORM (1W TOTAL POWER
CONSUMPTION)
s
INTERNALLY TRIMMED ZENER
REFERENCE
s
UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
s
INTEGRATED START-UP SUPPLY
s
AVALANCHE RUGGED
s
OVERTEMPERATURE PROTECTION
s
LOW STAND-BY CURRENT
s
ADJUSTABLE CURRENT LIMITATION
DESCRIPTION
VIPer20B
TM
combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (400V 1.3A).
Typical applications cover off line power supplies
with a secondary max power capability of 30W. It
is compatible from both primary or secondary
regulation loop despite using around 50% less
components when compared with a discrete
solution. Burst mode operation is an additional
feature of this device, offering the possibility to
operate
in
stand-by
mode
without
extra
components.
PENTAWATT HV
Power SO-10
1
10
1/17
ABSOLUTE MAXIMUM RATING
Symb ol
Parameter
Value
Uni t
V
DS
Continuous Drain-Source Voltage (T j = 25 to 125
o
C)
-0. 3 to 400
V
I
D
Maximum Current
Int ernally Limited
A
V
DD
Supply Voltage
0 t o 15
V
V
OSC
Voltage Range I nput
0 t o V
DD
V
V
COMP
Voltage Range I nput
0 to 5
V
I
COMP
Maximum Continuous Current
2
mA
V
esd
Elect rostatic discharge (R = 1. 5 K
C = 100pF)
2000
V
I
D(AR)
Avalanche Drain-Source Current , Repetitive or Not-Repetitive
(T
C
= 100
o
C, Pulse W idth Limited by T
J
max,
<1%)
T BD
A
P
tot
Power Dissipat ion at Tc = 25
o
C
57
W
T
j
Junct ion Operat ing Temperature
-40 to 140
o
C
T
s tg
St orage Temperature
-65 to 150
o
C
THERMAL DATA
R
t hj-ca se
Thermal Resistance Junction-case
Max
2.0
o
C/W
R
th j-a mb.
Thermal Resistance Junction-ambient
Max
70
o
C/W
CURRENT AND VOLTAGE CONVENTIONS
-
+
13V
OSC
COMP SOURCE
DR AIN
VD D
V
COMP
V
OSC
V
DD
V
DS
I
COMP
I
OSC
I
DD
I
D
FC00020
CONNECTION DIAGRAMS (Top View)
PENTAWATT HV
PowerSO-10
VIPer20B / VIPer20BSP
2/17
PINS FUNCTIONAL DESCRIPTION
DRAIN PIN:
Integrated power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation. The device
is able to handle an unclamped current during its
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.
SOURCE PIN:
Power MOSFET source pin. Primary side circuit
common ground connection.
VDD PIN :
This pin provides two functions :
-
It corresponds to the low voltage supply of the
control part of the circuit. If V
DD
goes below 8V,
the start-up current source is activated and the
output power MOSFET is switched off until the
V
DD
voltage reaches 11V. During this phase,
the internal current consumption is reduced,
the V
DD
pin is sourcing a current of about 1mA
and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
device tries to start up by switching again.
-
This pin is also connected to the error amplifier,
in order to allow primary as well as secondary
regulation configurations. In case of primary
regulation, an internal 13V trimmed reference
voltage is used to maintain V
DD
at 13V. For
secondary regulation, a voltage between 8.5V
and 12.5V will be put
on V
DD
pin by
transformer design, in order to stuck the output
of the transconductance amplifier to the high
state. The COMP pin behaves as a constant
current source, and can easily be connected to
the output of an optocoupler. Note that any
overvoltage due to regulation loop failure is still
detected by the error amplifier through the V
DD
voltage, which cannot overpass 13V. The
output voltage will be somewhat higher than
the nominal one, but still under control.
COMP PIN :
This pin provides two functions :
-
It is the output of the error transconductance
amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the
needed value with usual components value. As
stated
above,
secondary
regulation
configurations are also implemented through
the COMP pin.
-
When the COMP voltage is going below 0.5V,
the shut-down of the circuit occurs, with a zero
duty cycle for the power MOSFET. This feature
can be used to switch off the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or open load condition.
OSC PIN :
An R
T
-C
T
network must be connected on that pin
to define the switching frequency. Note that
despite the
connection of R
T
to V
DD
, no
significant frequency change occurs for V
DD
varying from 8V to 15V. It provides also a
synchronisation capability, when connected to an
external frequency source.
ORDERING NUMBERS
PENT AW ATT HV
PowerSO -10
VI Per20B
VIPer20BSP
VIPer20B / VIPer20BSP
3/17
ELECTRICAL CHARACTERISTICS (T
J
= 25
o
C, V
DD
= 13 V, unless otherwise specified)
POWER SECTION
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
BV
DSS
Drain-Source Voltage
I
D
= 10 mA
V
COMP
= 0 V
400
V
I
DSS
Of f-St ate Drain Current V
DS
= 300 V
T
J
= 125
o
C
V
COMP
= 0 V
0.6
mA
R
DS( on)
St atic Drain Source on
Resistance
I
D
= 0. 9 A
I
D
= 0. 9 A
T
J
= 100
o
C
7.3
8.7
15.7
t
f
Fall Time
I
D
= 0. 1 A
V
in
= 300 V (1)
(see fig. 3)
80
ns
t
r
Rise Time
I
D
= 0. 9 A
V
i n
= 300 V (1)
(see fig. 3)
50
ns
C
OSS
Output Capacit ance
V
DS
= 25 V
90
pF
(1) On Inductive Load, Clamped.
SUPPLY SECTION
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
I
DDch
St art -up Charging
Current
V
DD
= 0 to V
DDon
V
DS
= 70 V
(see fig. 2)
-2
mA
I
DD0
Operat ing Supply
Current
V
DD
= 12 V, F
SW
= 0 KHz
(see fig. 2)
12
T BD
mA
I
DD1
Operat ing Supply
Current
V
DD
= 12 V, F
SW
= 100 KHz
13
mA
I
DD2
Operat ing Supply
Current
V
DD
= 12 V, F
SW
= 200 KHz
14
mA
V
DDo ff
Undervolt age
Shutdown
(see fig. 2)
8
V
V
DDo n
Undervolt age Reset
(see fig. 2)
11
12
V
V
DDhyst
Hysteresis St art-up
(see fig. 2)
2. 4
3
V
OSCILLATOR SECTION
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
F
SW1
Oscillator Frequency
Initial Accuracy
R
T
= 8.2 K
C
T
=2. 4 nF
(see fig.7)
90
100
110
KHz
F
SW2
Oscillator Frequency
Total Variation
R
T
= 8.2 K
C
T
=2. 4 nF
V
DD
= 9 to15 V
T
J
= 0 t o 100
o
C
80
100
120
KHz
V
OSCih
Oscillator Peak Volt age
7.1
V
V
OSCi l
Oscillator Valley
Voltage
3.7
V
VIPer20B / VIPer20BSP
4/17
ELECTRICAL CHARACTERISTICS (continued)
ERROR AMPLIFIER SECTION
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
V
DDreg
VDD Regulation Point
I
COM P
= 0 mA
(see fig. 1)
12. 6
13
13.4
V
V
DDreg
Total Variation
T
J
= 0 t o 100
o
C
2
%
G
BW
Unity G ain Bandwidt h
From Input = V
DD
t o Out put = V
COMP
CO MP pin is open (see fig. 8)
150
KHz
A
VOL
Open Loop Voltage
Gain
CO MP pin is open (see fig. 8)
TBD
50
dB
G
m
DC T ransconductance
V
COMP
= 2.5 V
(see fig. 1)
TBD
1.5
T BD
mA/V
V
COMPL O
Output Low Level
I
COM P
= -400
A
V
DD
= 14 V
0.2
V
V
COMPHI
Output High Level
I
COM P
= 400
A
V
DD
= 12 V
4.5
V
I
COM PLO
Output Low Current
Capabilit y
V
COMP
= 2.5 V
V
DD
= 14 V
-600
A
I
COMPHI
Output High Current
Capabilit y
V
COMP
= 2.5 V
V
DD
= 12 V
600
A
PWM COMPARATOR SECTION
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
H
ID
V
COMP
/
I
Dpea k
V
COMP
= 1 t o 3 V
TBD
2.3
T BD
V/A
V
COMPof f
V
COMP
offset
I
Dp eak
= 10 mA
0.5
V
I
Dpeak
Peak Current Limit ation V
DD
= 12 V
COMP pin open
1. 3
T BD
A
t
d
Current Sense Delay
to turn-off
I
D
= 0. 4 A
250
ns
t
b
Blanking Time
300
ns
SHUTDOWN AND OVERTEMPERATURE SECTION
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
V
COMPth
Restart threshold
(see fig. 4)
0.5
V
t
DI Ssu
Disable Set Up T ime
(see fig. 4)
1.7
5
s
T
t sd
Thermal Shutdown
Temperature
(see fig. 6)
140
160
o
C
T
hyst
Thermal Shutdown
Hysteresis
(see fig. 6)
34
o
C
VIPer20B / VIPer20BSP
5/17
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