VIPer50/SP
VIPer50A/ASP
SMPS PRIMARY I.C.
May 1999
BLOCK DIAGRAM
F
C
0
0
2
9
1
V
DD
OSC
COMP
DRAIN
SOURCE
13 V
UVLO
LOGIC
SECURITY
LATCH
PWM
LATCH
FF
FF
R/S
S
Q
S
R1
R2 R3
Q
OSCILLATOR
OVERTEMP.
DETECTOR
ERROR
AMPLIFIER
_
+
0.5 V
+
_
1.7
s
DELAY
250 ns
BLANKING
CURRENT
AMPLIFIER
ON/OFF
0.5V
2 V/A
_
+
+
_
4.5 V
T YPE
V
DSS
I
n
R
DS(on)
VIPer50/SP
620V
1.5 A
5
VIPer50A/ASP
700V
1.5 A
5.7
FEATURE
s
ADJUSTABLE SWITCHING FREQUENCY UP
TO 200KHZ
s
CURRENT MODE CONTROL
s
SOFT START AND SHUT DOWN CONTROL
s
AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
"BLUE ANGEL" NORM (<1W TOTAL POWER
CONSUMPTION)
s
INTERNALLY TRIMMED ZENER
REFERENCE
s
UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
s
INTEGRATED START-UP SUPPLY
s
AVALANCHE RUGGED
s
OVERTEMPERATURE PROTECTION
s
LOW STAND-BY CURRENT
s
ADJUSTABLE CURRENT LIMITATION
DESCRIPTION
VIPer50
TM
/50A
make
using
VIPower
M0
Technology combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (620V or 700V / 1.5A).
Typical applications cover off line power supplies
with a secondary power capability of 25W in wide
range condition and 50W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50%
less
components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode without extra components.
PowerSO-10
1
10
PENTAWATT HV
PENTAWATT HV
(022Y)
1/20
ABSOLUTE MAXIMUM RATING
Symb ol
Parameter
Value
Uni t
V
DS
Continuous Drain-Source Voltage (Tj = 25 to 125
o
C)
for VIPer50/SP
for VIPer50A/ ASP
-0.3 to 620
-0.3 to 700
V
V
I
D
Maximum Current
I nternally Limited
A
V
DD
Supply Voltage
0 t o 15
V
V
OSC
Voltage Range Input
0 t o V
DD
V
V
COMP
Voltage Range Input
0 to 5
V
I
COMP
Maximum Cont inuous Current
2
mA
V
esd
Electrostatic discharge (R = 1. 5 K
C = 100pF)
4000
V
I
D(AR)
Avalanche Drain-Source Current, Repetit ive or Not-Repet itive
(T C = 100
o
C, Pulse Widt h Limit ed by T
J
max,
<1%)
for VIPer50/SP
for VIPer50A/ ASP
1.5
1
A
A
P
tot
Power Dissipation at T c = 25
o
C
60
W
T
j
Junct ion Operating Temperature
I nternally Limited
o
C
T
s tg
St orage Temperature
-65 t o 150
o
C
THERMAL DATA
PENT AW ATT-HV
Po werSO-10(*)
R
t hj-ca se
Thermal Resistance Junction-case
Max
1.9
1.9
o
C/W
R
th j-a mb.
Thermal Resistance Ambient -case
Max
60
50
o
C/W
(*) When mounted using the minimum recommended pad size on FR-4 board.
CURRENT AND VOLTAGE CONVENTIONS
-
+
13V
OSC
COMP SOURCE
DRAIN
VDD
V
COMP
V
OSC
V
DD
V
DS
I
COMP
I
OSC
I
DD
I
D
FC00020
CONNECTION DIAGRAMS (Top View)
PENTAWATT HV
PENTAWATT HV (022Y)
PowerSO-10
VIPer50/SP - VIPer50A/ASP
2/20
PINS FUNCTIONAL DESCRIPTION
DRAIN PIN:
Integrated power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation. The device
is able to handle an unclamped current during its
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.
SOURCE PIN:
Power MOSFET source pin. Primary side circuit
common ground connection.
VDD PIN :
This pin provides two functions :
-
It corresponds to the low voltage supply of the
control part of the circuit. If V
DD
goes below 8V,
the start-up current source is activated and the
output power MOSFET is switched off until the
V
DD
voltage reaches 11V. During this phase,
the internal current consumption is reduced,
the V
DD
pin is sourcing a current of about 2mA
and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
device tries to start up by switching again.
-
This pin is also connected to the error
amplifier, in order to allow primary as well as
secondary regulation configurations. In case of
primary regulation, an internal 13V trimmed
reference voltage is used to maintain V
DD
at
13V. For secondary regulation, a voltage
between 8.5V and 12.5V will be put on V
DD
pin
by transformer design, in order to stuck the
output of the transconductance amplifier to the
high state. The COMP pin behaves as a
constant current source, and can easily be
connected to the output of an optocoupler.
Note that any overvoltage due to regulation
loop failure is still detected by the error
amplifier through the V
DD
voltage, which
cannot overpass 13V. The output voltage will
be somewhat higher than the nominal one, but
still under control.
COMP PIN :
This pin provides two functions :
-
It is the output of the error transconductance
amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the
needed value with usual components value. As
stated
above,
secondary
regulation
configurations are also implemented through
the COMP pin.
-
When the COMP voltage is going below 0.5V,
the shut-down of the circuit occurs, with a zero
duty cycle for the power MOSFET. This feature
can be used to switch off the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or open load condition.
OSC PIN :
An R
T
-C
T
network must be connected on that pin
to define the switching frequency. Note that
despite the
connection of R
T
to V
DD
, no
significant frequency change occurs for V
DD
varying from 8V to 15V. It provides also a
synchronisation capability, when connected to an
external frequency source.
ORDERING NUMBERS
PENT AW ATT HV
PENTAW AT T HV (022Y)
Pow erSO-10
VIP er50
VIPer50A
VI Per50 (022Y)
VIPer50A (022Y)
VIPer50SP
VI Per50ASP
VIPer50/SP - VIPer50A/ASP
3/20
AVALANCHE CHARACTERISTICS
Symb ol
Parameter
Max Valu e
Uni t
I
D(a r)
Avalanche Current , Repet itive or Not -Repetitive
(pulse widt h limited by T
j
max,
< 1%)
for VIPer50/SP
for VIPer50A/ ASP
(see fig. 12)
1.5
1.0
A
A
E
(ar)
Single Pulse Avalanche Energy
(starting T
j
= 25
o
C, I
D
= I
D( ar)
)
(see fig. 12)
30
mJ
ELECTRICAL CHARACTERISTICS (T
J
= 25
o
C, V
DD
= 13 V, unless otherwise specified)
POWER SECTION
Symb ol
Parameter
T est Con ditio ns
Mi n.
Typ .
Max.
Un it
BV
DSS
Drain-Source Voltage
I
D
= 1 mA
V
CO MP
= 0 V
for VIPer50/SP
for VIPer50A/ASP
(see fig. 5)
620
700
V
V
I
DSS
Of f-St ate Drain Current
V
CO MP
= 0 V
T
J
= 125
o
C
V
DS
= 620 V
for VIPer50/SP
V
DS
= 700 V
for VIPer50A/ ASP
1
1
mA
mA
R
DS( on)
St atic Drain Source on
Resistance
I
D
= 1 A
for VIPer50/SP
for VIPer50A/ASP
I
D
= 1 A
T
J
= 100
o
C
for VIPer50/SP
for VIPer50A/ASP
4.0
4.6
5.0
5.7
9.0
10.3
t
f
Fall T ime
ID = 0.2 A
V
in
= 300 V (1)
(see fig. 3)
100
ns
t
r
Rise Time
I
D
= 1 A
V
i n
= 300 V (1)
(see fig. 3)
50
ns
C
OSS
Output Capacit ance
V
DS
= 25 V
120
pF
(1) On Inductive Load, Clamped.
SUPPLY SECTION
Symb ol
Parameter
T est Con ditio ns
Mi n.
Typ .
Max.
Un it
I
DDch
St art-up Charging
Current
V
DD
= 5 V
V
DS
= 70 V
(see fig. 2 and fig.15)
-2
mA
I
DD0
Operating Supply Current V
DD
= 12 V, F
SW
= 0 KHz
(see fig. 2)
12
16
mA
I
DD1
Operating Supply Current V
DD
= 12 V, F
SW
= 100 KHz
14
mA
I
DD2
Operating Supply Current V
DD
= 12 V, F
SW
= 200 KHz
16
mA
V
DDo ff
Undervoltage Shut down
(see fig. 2)
8
V
V
DDo n
Undervoltage Reset
(see fig. 2)
11
12
V
V
DDhyst
Hysteresis St art -up
(see fig. 2)
2. 4
3
V
VIPer50/SP - VIPer50A/ASP
4/20
ELECTRICAL CHARACTERISTICS (continued)
OSCILLATOR SECTION
Symb ol
Parameter
T est Con ditio ns
Mi n.
Typ .
Max.
Un it
F
SW
Oscillator F requency
Total Variation
R
T
= 8.2 K
C
T
=2.4 nF
V
DD
= 9 to15 V
with R
T
1%
C
T
5%
(see fig. 6 and fig.9)
90
100
110
KHz
V
OSCih
Oscillator Peak Volt age
7.1
V
V
OSCi l
Oscillator Valley Voltage
3.7
V
ERROR AMPLIFIER SECTION
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
V
DDreg
VDD Regulat ion Point
I
COM P
= 0 mA
(see f ig.1)
12. 6
13
13.4
V
V
DDreg
Total Variation
T
J
= 0 to 100
o
C
2
%
G
BW
Unity Gain Bandwidt h
From Input = V
DD
t o O utput = V
COM P
CO MP pin is open (see fig. 10)
150
KHz
A
VOL
Open Loop Voltage
Gain
CO MP pin is open (see fig. 10)
45
52
dB
G
m
DC T ransconduct ance
V
COMP
= 2.5 V
(see f ig. 1)
1. 1
1.5
1.9
mA/V
V
COMPL O
Output Low Level
I
COM P
= -400
A
V
DD
= 14 V
0.2
V
V
COMPHI
Output High Level
I
COM P
= 400
A
V
DD
= 12 V
4.5
V
I
COM PLO
Output Low Current
Capability
V
COMP
= 2.5 V
V
DD
= 14 V
-600
A
I
COMPHI
Output High Current
Capability
V
COMP
= 2.5 V
V
DD
= 12 V
600
A
PWM COMPARATOR SECTION
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
H
ID
V
COMP
/
I
Dpea k
V
COMP
= 1 to 3 V
1. 4
2
2.6
V/A
V
COMPof f
V
COMP
off set
I
Dp eak
= 10 mA
0.5
V
I
Dpeak
Peak Current Limitat ion V
DD
= 12 V
COMP pin open
1. 5
2
2.7
A
t
d
Current Sense Delay
to turn-off
I
D
= 0. 5 A
250
ns
t
b
Blanking Time
250
360
ns
t
on( mi n)
Minimum on T ime
350
ns
SHUTDOWN AND OVERTEMPERATURE SECTION
Symb ol
Parameter
Test Cond ition s
Mi n.
Typ .
Max.
Un it
V
COMPth
Restart threshold
(see f ig. 4)
0.5
V
t
DI Ssu
Disable Set Up Time
(see f ig. 4)
1.7
5
s
T
t sd
Thermal Shutdown
Temperat ure
(see f ig. 8)
140
170
o
C
T
hyst
Thermal Shutdown
Hysteresis
(see f ig. 8)
40
o
C
VIPer50/SP - VIPer50A/ASP
5/20
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