October 1999
1/14
VNP49N04FI
/
VNB49N04 / VNV49N04
"OMNIFET":
FULLY AUTOPROTECTED POWER MOSFET
1
n
LINEAR CURRENT LIMITATION
n
THERMAL SHUT DOWN
n
SHORT CIRCUIT PROTECTION
n
INTEGRATED CLAMP
n
LOW CURRENT DRAWN FROM INPUT PIN
n
DIAGNOSTIC FEEDBACK THROUGH INPUT
PIN
n
ESD PROTECTION
n
DIRECT ACCESS TO THE GATE OF THE
POWER MOSFET (ANALOG DRIVING)
n
COMPATIBLE WITH STANDARD POWER
MOSFET
DESCRIPTION
The VNP49N04FI, VNB49N04, VNV49N04 are
monolithic
devices
designed
in
STMicroelectronics
VIPower
M0
Technology,
intended for replacement of standard Power
MOSFETS from DC up to 50KHz applications.
Built-in thermal shutdown, linear current limitation
and overvoltage clamp protect the chip in harsh
environments.
Fault feedback can be detected by monitoring the
voltage at the input pin.
TYPE
V
CLAMP
R
DS(ON)
I
LIM
VNP49N04FI
VNB49N04
VNV49N04
42 V
20 m
49 A
PowerSO-10
TM
TO-263 (D2PAK)
ORDER CODES:
ISOWATT220
VNP49N04FI
PowerSO-10
TM
VNV49N04
TO-263 (D2PAK)
VNB49N04
1
10
1
2
3
1
3
ISOWATT220
Overvoltage
Gate
Linear
DRAIN
SOURCE
Clamp
Current
Limiter
Control
Over
Temperature
INPUT
BLOCK DIAGRAM
Status
2/14
VNP49N04FI / VNB49N04 / VNV49N04
ABSOLUTE MAXIMUM RATING
CONNECTION DIAGRAM (TOP VIEW)
Symbol
Parameter
Value
Unit
PowerSO-10
TM
D2PAK
ISOWATT220
V
DS
Drain-source Voltage (V
IN
=0V)
Internally Clamped
V
V
IN
Input Voltage
18
V
I
D
Drain Current
Internally Limited
A
I
R
Reverse DC Output Current
-50
A
V
ESD
Electrostatic Discharge (R=1.5K
, C=100pF)
2000
V
P
tot
Total Dissipation at T
c
=25
C
125
125
40
W
T
j
Operating Junction Temperature
Internally limited
C
T
c
Case Operating Temperature
Internally limited
C
T
stg
Storage Temperature
-55 to 150
C
1
1
2
3
4
5
6
7
8
9
10
11
DRAIN
SOURCE
SOURCE
N.C.
SOURCE
SOURCE
INPUT
INPUT
INPUT
INPUT
INPUT
PowerSO-10
TM
D2PAK
SOURCE
DRAIN
INPUT
3
2
1
3
2
1
INPUT
DRAIN
SOURCE
ISOW ATT220
3/14
VNP49N04FI / VNB49N04 / VNV49N04
THERMAL DATA
ELECTRICAL CHARACTERISTICS (-40
C < T
j
< 125
C, unless otherwise specified)
OFF
ON (*)
DYNAMIC
SWITCHING (**)
Symbol
Parameter
Value
Unit
PowerSO-10
D2PAK
ISOW ATT220
R
thj-case
Thermal Resistance Junction-case
}}}
MAX
1
1
3.12
C/W
R
thj-amb
Thermal Resistance Junction-ambient
MAX
50
62.5
62.5
C/W
Symbol
Parameter
Test Condit ions
Min
Typ
Max
Unit
V
CLAMP
Drain-source Clamp
Voltage
I
D
=200 mA; V
IN
=0
34
42
50
V
V
CLTH
Drain-source Clamp
Threshold Voltage
I
D
=2mA; V
IN
=0
33
V
V
INCL
Input-Source Reverse
Clamp Voltage
I
IN
= -1mA
-1.2
-0.1
V
I
DSS
Zero Input Voltage Drain
Current (V
IN
=0V)
V
DS
=13V; V
IN
=0V
V
DS
=25V; V
IN
=0V
70
220
A
A
I
ISS
Supply Current from Input
Pin
V
DS
=0V; V
IN
=10V
250
550
A
Symbol
Parameter
Test Condit ions
Min
Typ
Max
Unit
V
IN(th)
Input Threshold Voltage
V
DS
=V
IN;
I
D
+ I
IN
=1mA
0.8
3
V
R
DS(on)
Static Drain-source On
Resistance
V
IN
=10V; I
D
=25A
V
IN
=5V; I
D
=25A
0.04
0.05
Symbol
Parameter
Test Condit ions
Min
Typ
Max
Unit
g
fs
(*)
Forward
Transconductance
V
DS
=13V; I
D
=25A;
T
c
=25
C
25
30
S
C
OSS
Output Capacitance
V
DS
=13V; f=1MHz; V
IN
=0V;
T
c
=25
C
1100
1500
pF
Symbol
Parameter
Test Condi tions
Min
Typ
Max
Unit
t
d(on)
Turn-on Delay Time
V
DS
=15V; I
D
=25A
V
gen
=10V; R
gen
=10
(see figure 3)
200
600
ns
t
r
Rise Time
1300
3600
ns
t
d(off)
Turn-off Delay Time
800
2400
ns
t
f
Fall Time
300
900
ns
t
d(on)
Turn-on Delay Time
V
DS
=15V; I
D
=25A
V
gen
=10V; R
gen
=1000
(see figure 3)
1.3
3.8
s
t
r
Rise Time
3.8
10.4
s
t
d(off)
Turn-off Delay Time
12
24
s
t
f
Fall Time
6.1
17
s
(di/dt)
on
Turn-on Current Slope
V
DS
=15V; I
D
=25A
V
IN
=10V; R
gen
=10
25
A/
s
Q
i
Total Input Charge
V
DS
=15V; I
D
=25A; V
IN
=10V
100
nC
1
4/14
VNP49N04FI / VNB49N04 / VNV49N04
SOURCE DRAIN DIODE
PROTECTIONS
(*) Pulsed: Pulse duration = 300
s, duty cycle 1.5%
(**) Parameters guaranteed by design/characterization
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
SD
(*)
Forward On Voltage
I
SD
=25A; V
IN
=0V
1.8
V
t
rr
(**)
Reverse Recovery Time
I
SD
=25A; di/dt=100A/
s
V
DS
=30V; T
j
=25
C
(see test circuit, figure 5)
250
ns
Q
rr
(**)
Reverse Recovery Charge
910
nC
I
RRM
(**)
Reverse Recovery Current
7.5
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
I
LIM
Drain Current Limit
V
IN
=10V; V
DS
=13V
V
IN
=5V; V
DS
=13V
28
28
49
49
70
70
A
A
t
dlim
(**)
Step Response Current
Limit
V
IN
=10V
V
IN
=5V
35
90
50
150
s
s
T
jsh
(**)
Overtemperature
Shutdown
150
C
T
jrs
(**)
Overtemperature Reset
135
C
I
gf
(**)
Fault Sink Current
V
IN
=10V; V
DS
=13V
V
IN
=5V; V
DS
=13V
50
20
mA
mA
E
as
(**)
Single Pulse
Avalanche Energy
Starting T
j
=25
C; V
DS
=20V
V
IN
=10V; R
gen
=1K
;
L=6mH
4
J
2
5/14
VNP49N04FI / VNB49N04 / VNV49N04
PROTECTION FEATURES
During normal operation, the INPUT pin is
electrically connected to the gate of the internal
power MOSFET. The device then behaves like a
standard power MOSFET and can be used as a
switch from DC up to 50KHz. The only difference
from the user's standpoint is that a small DC
current (I
ISS
) flows into the INPUT pin in order to
supply the internal circuitry.
The device integrates:
- OVERVOLTAGE CLAMP PROTECTION:
internally set at 42V, along with the rugged
avalanche characteristics of the Power MOSFET
stage give this device unrivalled ruggedness and
energy handling capability. This feature is mainly
important when driving inductive loads.
- LINEAR CURRENT LIMITER CIRCUIT:
limits the drain current I
D
to I
LIM
whatever the
INPUT pin voltage. When the current limiter is
active, the device operates in the linear region, so
power dissipation may exceed the capability of the
heatsink. Both case and junction temperatures
increase, and if this phase lasts long enough,
junction
temperature
may
reach
the
overtemperature threshold T
jsh
.
- OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION:
these are based on sensing the chip temperature
and are not dependent on the input voltage. The
location of the sensing element on the chip in the
power stage area ensures fast, accurate detection
of the junction temperature. Overtemperature
cutout occurs at minimum 150
C. The device is
automatically restarted when the chip temperature
falls below 135
C.
- STATUS FEEDBACK:
in the case of an overtemperature fault condition, a
status feedback is provided through the INPUT
pin. The internal protection circuit disconnects the
input from the gate and connects it instead to
ground via an equivalent resistance of 100
.
The
failure can be detected by monitoring the voltage
at the INPUT pin, which will be close to ground
potential. Additional features of this device are
ESD protection according to the Human Body
model and the ability to be driven from a TTL Logic
circuit (with a small increase in
R
DS(ON)
).
1
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