February 2003
1/14
VNS3NV04D
"OMNIFET II":
FULLY AUTOPROTECTED POWER MOSFET
1
n
LINEAR CURRENT LIMITATION
n
THERMAL SHUT DOWN
n
SHORT CIRCUIT PROTECTION
n
INTEGRATED CLAMP
n
LOW CURRENT DRAWN FROM INPUT PIN
n
DIAGNOSTIC FEEDBACK THROUGH INPUT
PIN
n
ESD PROTECTION
n
DIRECT ACCESS TO THE GATE OF THE
POWER MOSFET (ANALOG DRIVING)
n
COMPATIBLE WITH STANDARD POWER
MOSFET
DESCRIPTION
The VNS3NV04D is a device formed by two
monolithic OMNIFET II chips housed in a
standard SO-8 package. The OMNIFET II are
designed in STMicroelectronics VIPower M0-3
Technology: they are intended for replacement of
standard Power MOSFETS from DC up to 50KHz
applications. Built in thermal shutdown, linear
current limitation and overvoltage clamp protects
the chip in harsh environments.
Fault feedback can be detected by monitoring the
voltage at the input pin.
TYPE
R
DS(on)
I
lim
V
clamp
VNS3NV04D
120 m
(*)
3.5 A (*)
40 V (*)
SO-8
BLOCK DIAGRAM
SOURCE2
OVERVOLTAGE
LINEAR
DRAIN1
SOURCE1
CLAMP
CURRENT
LIMITER
OVER
TEMPERATURE
GATE
CONTROL
DRAIN2
OVERVOLTAGE
CLAMP
LINEAR
CURRENT
LIMITER
GATE
CONTROL
OVER
TEMPERATURE
INPUT2
INPUT1
(*)Per each device
2/14
VNS3NV04D
ABSOLUTE MAXIMUM RATING
CONNECTION DIAGRAM (TOP VIEW)
Symbol
Parameter
Value
Unit
V
DSn
Drain-source Voltage (V
INn
=0V)
Internally Clamped
V
V
INn
Input Voltage
Internally Clamped
V
I
INn
Input Current
+/-20
mA
R
IN MINn
Minimum Input Series Impedance
220
I
Dn
Drain Current
Internally Limited
A
I
Rn
Reverse DC Output Current
-5.5
A
V
ESD1
Electrostatic Discharge (R=1.5K
, C=100pF)
4000
V
V
ESD2
Electrostatic Discharge on output pins only (R=330
, C=150pF)
16500
V
P
tot
Total Dissipation at T
c
=25C
4
W
T
j
Operating Junction Temperature
Internally limited
C
T
c
Case Operating Temperature
Internally limited
C
T
stg
Storage Temperature
-55 to 150
C
1
CURRENT AND VOLTAGE CONVENTIONS
DRAIN 2
DRAIN 1
DRAIN 2
DRAIN 1
INPUT 2
SOURCE 1
SOURCE 2
INPUT 1
1
4
5
8
DRAIN 1
INPUT 1
SOURCE 2
I
IN1
V
IN1
INPUT 2
I
IN2
SOURCE 1
DRAIN 2
V
IN2
I
D2
I
D1
V
DS1
V
DS1
R
IN1
R
IN2
3/14
VNS3NV04D
THERMAL DATA
(*)
When mounted on a standard single-sided FR4 board with 50mm
2
of Cu (at least 35
m thick) connected to all DRAIN pins of the relative
channel.
ON
Symbol
Parameter
Value
Unit
R
thj-lead
Thermal Resistance Junction-lead (per channel)
MAX
30
C/W
R
thj-amb
Thermal Resistance Junction-ambient
MAX
80(*)
C/W
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
CLAMP
Drain-source Clamp
Voltage
V
IN
=0V; I
D
=1.5A 40
45
55
V
V
CLTH
Drain-source Clamp
Threshold Voltage
V
IN
=0V; I
D
=2mA 36
V
V
INTH
Input Threshold Voltage
V
DS
=V
IN
; I
D
=1mA
0.5
2.5
V
I
ISS
Supply Current from Input
Pin
V
DS
=0V; V
IN
=5V 100
150
A
V
INCL
Input-Source Clamp
Voltage
I
IN
=1mA
I
IN
=-1mA
6
-1.0
6.8
8
-0.3
V
I
DSS
Zero Input Voltage Drain
Current (V
IN
=0V)
V
DS
=13V; V
IN
=0V; T
j
=25C
V
DS
=25V; V
IN
=0V
30
75
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
R
DS(on)
Static Drain-source On
Resistance
V
IN
=5V; I
D
=1.5A; T
j
=25C
V
IN
=5V; I
D
=1.5A
120
240
m
ELECTRICAL CHARACTERISTICS (-40C < T
j
< 150C, unless otherwise specified)
OFF
(Per each device)
1
4/14
VNS3NV04D
ELECTRICAL CHARACTERISTICS (continued) (T
j
=25C, unless otherwise specified)
DYNAMIC
SWITCHING
SOURCE DRAIN DIODE
PROTECTIONS (-40C < T
j
< 150C, unless otherwise specified)
(*) Pulsed: Pulse duration = 300
s, duty cycle 1.5%
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
g
fs
(*)
Forward
Transconductance
V
DD
=13V; I
D
=1.5A
5.0
S
C
OSS
Output Capacitance
V
DS
=13V; f=1MHz; V
IN
=0V 150
pF
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
t
d(on)
Turn-on Delay Time
V
DD
=15V; I
D
=1.5A
V
gen
=5V; R
gen
=R
IN MINn
=220
(see figure 1)
90
300
ns
t
r
Rise Time
250
750
ns
t
d(off)
Turn-off Delay Time
450
1350
ns
t
f
Fall Time
250
750
ns
t
d(on)
Turn-on Delay Time
V
DD
=15V; I
D
=1.5A
V
gen
=5V; R
gen
=2.2K
(see figure 1)
0.45
1.35
s
t
r
Rise Time
2.5
7.5
s
t
d(off)
Turn-off Delay Time
3.3
10.0
s
t
f
Fall Time
2.0
6.0
s
(dI/dt)
on
Turn-on Current Slope
V
DD
=15V; I
D
=1.5A
V
gen
=5V; R
gen
=R
IN MINn
=220
4.7
A/
s
Q
i
Total Input Charge
V
DD
=12V; I
D
=1.5A; V
IN
=5V
I
gen
=2.13mA (see figure 5)
8.5
nC
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
SD
(*)
Forward On Voltage
I
SD
=1.5A; V
IN
=0V
0.8
V
t
rr
Reverse Recovery Time
I
SD
=1.5A; dI/dt=12A/
s
V
DD
=30V; L=200
H
(see test circuit, figure 2)
107
ns
Q
rr
Reverse
Recovery
Charge
37
C
I
RRM
Reverse
Recovery
Current
0.7
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
I
lim
Drain Current Limit
V
IN
=5V; V
DS
=13V 3.5
5
7
A
t
dlim
Step Response Current
Limit
V
IN
=5V; V
DS
=13V
10
s
T
jsh
Overtemperature
Shutdown
150
175
200
C
T
jrs
Overtemperature
Reset
135
C
I
gf
Fault Sink Current
V
IN
=5V; V
DS
=13V; T
j
=T
jsh
10
15
20
mA
E
as
Single Pulse
Avalanche Energy
starting T
j
=25C; V
DD
=24V
V
IN
=5V; R
gen
=R
IN MINn
=220
;
L=24mH
(see figures 3 & 4)
100
mJ
2
5/14
VNS3NV04D
PROTECTION FEATURES
During normal operation, the INPUT pin is
electrically connected to the gate of the internal
power MOSFET through a low impedance path.
The device then behaves like a standard power
MOSFET and can be used as a switch from DC to
50KHz. The only difference from the user's
standpoint is that a small DC current I
ISS
(typ.
100
A) flows into the INPUT pin in order to supply
the internal circuitry.
The device integrates:
- OVERVOLTAGE CLAMP PROTECTION:
internally set at 45V, along with the rugged
avalanche characteristics of the Power MOSFET
stage give this device unrivalled ruggedness and
energy handling capability. This feature is mainly
important when driving inductive loads.
- LINEAR CURRENT LIMITER CIRCUIT: limits
the drain current I
D
to I
lim
whatever the INPUT pin
voltage. When the current limiter is active, the
device operates in the linear region, so power
dissipation may exceed the capability of the
heatsink. Both case and junction temperatures
increase, and if this phase lasts long enough,
junction temperature may reach the
overtemperature threshold T
jsh
.
- OVERTEMPERATURE AND SHORT CIRCUIT
PROTECTION: these are based on sensing the
chip temperature and are not dependent on the
input voltage. The location of the sensing element
on the chip in the power stage area ensures fast,
accurate detection of the junction temperature.
Overtemperature cutout occurs in the range 150 to
190 C, a typical value being 170 C. The device is
automatically restarted when the chip temperature
falls of about 15C below shut-down temperature.
- STATUS FEEDBACK: in the case of an
overtemperature fault condition (T
j
> T
jsh
), the
device tries to sink a diagnostic current I
gf
through
the INPUT pin in order to indicate fault condition. If
driven from a low impedance source, this current
may be used in order to warn the control circuit of
a device shutdown. If the drive impedance is high
enough so that the INPUT pin driver is not able to
supply the current I
gf
, the INPUT pin will fall to 0V.
This will not however affect the device
operation: no requirement is put on the current
capability of the INPUT pin driver except to be
able to supply the normal operation drive
current I
ISS
.
Additional features of this device are ESD
protection according to the Human Body model
and the ability to be driven from a TTL Logic
circuit.
1
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