1
Characteristics subject to change without notice
2079 1.2 05/24/04
SMS45
SUMMIT
MICROELECTRONICS, Inc.
SUMMIT MICROELECTRONICS, Inc., 2004 1717 Fox Dr. San Jose, CA 95131 Phone 408-436-9890 FAX 408-436-9897
www.summitmicro.com
PRELIMINARY INFORMATION
1
(SEE LAST PAGE)
Operational from any of four Voltage Monitoring
Inputs
Programmable Power-up Cascade Sequencing
Programmability allows monitoring any voltage
between 0.6V and 5.6V with no external
components
Programmable 5mV steps in the low range
Programmable Watchdog Timer
Programmable Reset Pulse Width
Programmable Nonvolatile Combinatorial Logic
for generation of Reset
Fault Status Register
4k-Bit Nonvolatile General Purpose Memory
APPLICATIONS
Desktop/Notebook/Tablet Computers
Multi-voltage Systems
Telecom/Network Servers
Portable Battery-powered Equipment
Set-top Boxes
Data-storage Equipment
Quad Programmable Precision Cascade Sequencer and Supervisory
Controller with
4k-Bit Nonvolatile Memory
FEATURES
INTRODUCTION
The SMS45 is a nonvolatile user-programmable voltage
supply cascade sequencer and supervisory circuit de-
signed specifically for advanced systems that need to
monitor multiple voltages. The SMS45 can monitor four
separate voltages without the need of any external voltage
divider circuitry unlike other devices that need factory-
trimmed threshold voltages and external components to
accommodate different supply voltages and tolerances.
The SMS45 can also be used to enable DC/DC converters
or LDOs to provide a closed loop cascading of the supplies
during power -up.
The SMS45 watchdog timer has a user programmable
time-out period and it can be placed in an idle mode for
system initialization or system debug. All of the functions
are user accessible through an industry standard I
2
C 2-wire
serial interface.
Programming of configuration, control and calibration
values by the user is simplified with the SMX3200 interface
adapter and Windows GUI software obtainable from Sum-
mit Microelectronics.
SIMPLIFIED APPLICATION DRAWING
Applications Schematic using the SMS45 Controller to provide closed loop power-up cascade sequenc-
ing and supervisory functions.
NOTE: THIS IS AN APPLICATIONS EXAMPLE ONLY. SOME PINS, COMPONENTS AND VALUES ARE NOT SHOWN.
V0
V1
V2
V3
RESET#
PUP#1
VDD_CAP
PUP#2
PUP#3
I
2
C
5V
3.3V
2.5V
1.8V
DC-DC
DC-DC
LDO
SMS45
A2
A1 SDA SCL
7
6
9
10
1
16
2
3
14
MR#
Reset#
15
WLDI
GND
8
11
12
4
13
5
0.1F
2
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
INTERNAL BLOCK DIAGRAM
Time based sequencing has the ability to turn supplies on
in a specific order. However, it cannot guarantee that each
supply has reached valid voltage levels before the next
supply is sequenced on. Cascade sequencing guarantees
the supplies are enabled a programmed period of time after
the previous voltage has reached its minimum pro-
grammed valid level. Figure 1 shows that each succeeding
voltage must reach its minimum valid level before the timer
is started to time the interval, t, for the next voltage. The
duration of each t is programmable for each supply to
supply transition. The next supply is not enabled until the
timer has elapsed. See also Figure 5.
Figure 1. Cascading Power Supplies
CASCADE SEQUENCING
0V
4V
2V
6V
T
t
t
t
5V
2.5V
3.3V
1.8V
5V Valid
3.3V Valid
2.5V Valid
2047 Fig01
V
+
REF
NV DAC
+
REF
NV DAC
+
REF
NV DAC
+
REF
NV DAC
V0
16
V1
2
V2
3
V3
14
MR#
1
PROGRAMMABLE
WATCHDOG
TIMER
PROGRAMMABLE
RESET PULSE
GENERATOR
SERIAL
BUS
CONTROL
LOGIC
4K-BIT NV
MEMORY
RESET#
PUP#1
11
5
4
SDA
VDD_CAP
WLDI
9
15
10
PUP#2
PUP#3
13
SCL
A2
7
6
A1
CONFIGURATION
REGISTER
CONFIGURATION
REGISTER
GND
8
PROGRAMMABLE
POWER
CASCADING
VDD_CAP
50k
50k
12
SUPPLY
ARBITRATION
V3
V2
V1
V0
VDD_CAP
3
2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
PIN CONFIGURATION
PIN NAMES
2047 Pins Table 2.0
MR#
V
1
V
2
PUP#1
PUP#2
A1
A2
GND
V
0
WLDI
V
3
PUP#3
VDD_CAP
RESET#
SCL
SDA
2047 PCon 2.0
1
2
3
4
5
6
7
8
16
15
14
13
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11
10
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4
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
*Note -
Stresses beyond the listed Absolute Maximum Ratings may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Temperature Under Bias ...................... 55C to 125C
Storage Temperature ............................. 65C to 150C
Lead Solder Temperature (10s) ........................... 300 C
Terminal Voltage with Respect to GND:
V
0
, V
1
, V
2
, and V
3
......... 0.3V to 6.0V
All Others ....................... 0.3V to 6.0V
Junction Temperature........................................150C
ESD Rating per JEDEC...................................2000V
Latch-Up testing per JEDEC...........................100mA
DC OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
RECOMMENDED OPERATING CONDITIONS
(Over Recommended Operating Conditions; Voltages are relative to GND)
Industrial Temperature Range............... 40
C to +85
C.
Commercial Temperature Range..............5
C to +70
C.
V
SUPPLY
Supply Voltage............................2.7V to 5.5V
V
SUPPLY
= Device supply voltage provided by the
highest V
X
input.
Package Thermal Resistance (
JA)
16 Lead SSOP.........................................23
o
C/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
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RELIABILITY CHARACTERISTICS
Data Retention.........................................100 Years
Endurance........................................100,000 Cycles
Note 1: Low Range Hysteresis = 4.2 X (Vtrip - 0.5 volts) mV. For Vtrip = 1.0 volts, Hysteresis = 2.1 mV (0.21 %),
High Range Hysteresis = 12.6 X (Vtrip -0.5 volts) mV. For Vtrip = 5.0 volts, Hysteresis = 56.7 mV (1.13%).
5
2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
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AC OPERATING CHARACTERISTICS
(Over Recommended Operating Conditions; Voltages are relative to GND, also see configuration registers)
6
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
PIN DESCRIPTIONS
V
0
, V
1
, V
2
, V
3
(16, 2, 3, 14)
These inputs are used as the voltage monitor inputs and
as the voltage supply for the SMS45. Internally they are
diode ORed and the input with the highest voltage
potential will be the default supply voltage (VDD_CAP).
The RESET# output will be valid if any one of the four inputs
is above 1V. However, for full device operation at least one
of the inputs must be at 2.7V or higher.
The sensing threshold for each input is independently
programmable in 5mV increments from 0.6V to 1.875V or
15mV increments from 1.8V to 5.625V. Also, the occur-
rence of an under- or over-voltage condition that is detected
as a result of the threshold setting can be used to generate
a RESET#. The programmable nature of the threshold
voltage eliminates the need for external voltage divider
networks.
GND
Power supply return.
MR# (1)
The manual reset input always generates a RESET#
output whenever it is driven low. The duration of the
RESET# output pulse will be initiated when MR# goes low
and it will stay low for the duration of MR# low plus the
programmed reset time-out period (t
PRTO
). If MR# is
brought low during a power-on cascade of the PUP#s the
cascade will be halted for the reset duration, and will then
resume from the point at which it was interrupted. MR#
must be held low during a configuration register write. This
signal is pulled up internally through a 50k
resistor.
RESET# (11)
The reset output is an active low open drain output. It will
be driven low whenever the MR# input is low or whenever
an enabled under-voltage or over-voltage condition exists.
The four voltage monitor inputs are always functioning, but
their ability to generate a reset is programmable (configu-
Figure 2. RESET# Timing with MR#
ration register 4). Refer to Figures 2 and 3 for a detailed
illustration of the relationship between MR#, RESET# and
the V
IN
levels.
VDD_CAP (12)
The VDD_CAP pin connects to the internal supply voltage
for the SMS45. A capacitor is placed on this pin to filter
supply noise as well as hold up the device in the event of
power failure. The voltage on this node is determined by the
highest input voltage. Loading of this pin should be
minimized to prevent excessive power dissipation in the
part.
WLDI (15)
Watchdog timer input. A high-to-low transition on the WLDI
input will clear the watchdog timer, effectively starting a
new time-out period. This signal is pulled up internally
through a 50k
resistor.
If WLDI is stuck low and no high-to-low transition is
received within the programmed t
PWDTO
period (pro-
grammed watchdog time-out) RESET# will be driven low.
Refer to Figure 4 for a detailed illustration.
Holding WLDI low will not block the watchdog from timing
out and generating a reset. Refer to Figure 4 for a detailed
illustration of the relationship between RESET# and WLDI.
tPRTO
2047 Fig04 3.0
RESET#
WLDI
t0
t0
t0
t0
t0
tPRTO
tPWDTO
tPWDTO
Figure 3. RESET# Timing
Figure 4. Watchdog and WLDI Timing
RESET#
tPRTO
V
0
-- V
3
tDRST
VPTH-UV
MR#
RESET#
tDMRRST
tPRTO
7
2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
A1,A2 (6, 7)
A1 and A2 are the address inputs. When addressing the
SMS45 memory or configuration registers the address
inputs distinguish which one of four possible devices
sharing the common bus is being addressed.
SDA (9)
SDA is the serial data input/output pin. It should be tied to
VDD_CAP through a pull-up resistor.
SCL (10)
SCL is the serial clock input. It should be tied to VDD_CAP
through a pull-up resistor.
PUP#1, PUP#2, PUP#3 (4, 5, 13)
These are the power-up permitted (PUP) active low open
drain outputs. The PUP pins are used when the SMS45 is
programmed to provide the cascade sequencing of LDOs
or DC/DC converters (see Figures 1 and 5 for illustra-
tions of cascading). Each delay is independently enabled
and programmable for its duration (configuration register
7). If all PUP# outputs are enabled the order of events
would be as follows: V
0
above threshold then delay to
PUP#1 turning on; V
1
above threshold then delay to PUP#2
turning on; V
2
above threshold then delay to PUP#3 turning
on. The delays are programmable.
PIN DESCRIPTIONS (CONTINUED)
8
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Figure 5. V
X
Input and Resulting PUP# Cascade (RESET# set to trip on V
3
Undervoltage)
Figure 6. Timing with Register 7 Contents 22
HEX
RESET#
V
0
VPTH0
V
1
PUP1#
V
2
PUP2#
V
3
PUP3#
VPTH1
VPTH2
tPRTO
tPDLY1
tPDLY2
tPDLY3
2047 Fig05
V0
VPTH0
V1
PUP1#
V2
PUP2#
PUP3#
50ms
50ms
VPTH2
2047 Fig06
DEVICE OPERATION
9
2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Figure 7. Cascade Flow Chart
Yes
No
Cascading
Enabled
V
0
>V
PTH
?
Turn On PUP#1
2047 Fig07
t
PDLY1
Yes
No
V1
>V
PTH
?
Turn On PUP#2
t
PDLY2
Yes
No
V2
>V
PTH
?
Turn On PUP#3
t
PDLY3
DEVICE OPERATION (CONTINUED)
10
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Table 2. Configuration Register 4
CONFIGURATION REGISTERS
SUPPLY AND MONITOR FUNCTIONS
The V
0
, V
1
, V
2,
and V
3
inputs are internally diode-ORed so
that any one of the four can act as the device supply. The
RESET# output will be guaranteed true so long as one of
the four pins is at or above 1V.
Note: for performing a memory operation (Read
or Write) and to have the ability to change
configuration register contents at least one sup-
ply input must be above 2.7V.
Read/Write operations require a 0.1F capacitor from the
VDD_CAP node to GND. For optimum performance
connect capacitors from each of the Vx inputs to GND.
Locate the capacitors as physically close to the SMS45 as
possible.
If cascading is enabled, the designer must insure V
0
is the
primary supply and is the first to become active.
Associated with each input is a comparator with a program-
mable threshold for detection of under-voltage or over-
voltage conditions on any of the four supply inputs. The
threshold can be programmed in 5mV increments any-
where within the range of 0.6V to 1.875V or 15mV incre-
ments within the range of 1.8V to 5.625V. Configuration
registers 0, 1, 2, and 3 adjust the thresholds for V
0
, V
1
, V
2,
and V
3
respectively.
If the value contained in any register is all zeroes, the
corresponding threshold will be 0.6V. If the contents were
low range 05
HEX
the threshold would then be 0.625V [0.6V
+ (5
0.005V)]. All four registers are configured as 8-Bit
registers.
Table 1. Configuration Registers 0, 1, 2, and 3
RESET FUNCTION AND THRESHOLD RANGE
The reset output has four programmable sources for
activation. Configuration register 4 is used for selecting the
activation source (D7:4), which can be any combination of
V
0
, V
1
, V
2
and V
3
. A monitor input can be programmed to
activate on either an under-voltage or over-voltage condi-
tion. The low-order four bits of configuration register 5
program these options. The reset threshold voltage range
for V0 to V3 can be set for 5mV increments below 1.875V
(low Range = "0") or for 15mV increments above 1.8V (high
range = "1") using Bits D3:0.
The RESET# output will become active when triggered by
a selected activation source such as an under-voltage
condition on V1. When this condition ceases, the RESET#
output will remain active for t
PRTO
(programmable reset
time-out). This reset time-out interval takes priority over
the PUP outputs for use of the timer.
The RESET# output has two hardwired sources for activa-
tion: the MR# input, and the expiration of the Watchdog
timer. RESET# will remain active so long as MR# is low,
and will continue driving the RESET# output for t
PRTO
(programmable reset time out) after MR# returns high. The
MR# input cannot be bypassed or disabled.
Refer to Figures 2, 3 and 4 for a detailed illustration of the
relationships among the affected signals.
The status of the four supplies is available at any time over
the I
2
C bus in the high order configuration bits of register 5
(Table 3). A "1" in a bit location indicates a fault on that
supply.
7
D
B
S
M
6
D
5
D
4
D
3
D
2
D
1
D
0
D
B
S
L
n
o
i
t
c
A
1
1
1
1
1
1
1
1
V
5
2
6
.
5
=
t
n
e
m
t
s
u
j
d
a
d
l
o
h
s
e
r
h
t
t
s
e
h
g
i
H
)
e
g
n
a
R
h
g
i
H
(
0
0
0
0
0
0
0
0
V
6
.
0
=
t
n
e
m
t
s
u
j
d
a
d
l
o
h
s
e
r
h
t
t
s
e
w
o
L
)
e
g
n
a
R
w
o
L
(
0
0
0
0
0
1
1
0
6
(
+
V
6
.
0
=
d
l
o
h
s
e
r
h
T
V
5
2
6
.
0
=
)
V
5
0
0
.
0
)
.
g
.
e
(
7
D
B
S
M
6
D
5
D
4
D
3
D
2
D
1
D
0
D
B
S
L
n
o
i
t
c
A
X
X
X
X
V
3
V
2
V
1
V
0
e
l
b
a
n
E
r
e
g
g
i
r
T
T
E
S
E
R
e
g
n
a
R
d
l
o
h
s
e
r
h
T
e
g
a
t
l
o
V
t
c
e
l
e
S
0
0
0
0
w
o
L
e
g
n
a
R
1
1
1
1
h
g
i
H
e
g
n
a
R
11
2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Table 5. Configuration Register 6 (D3 through D7)
Note 1 - Read Only bit D7 is set to a 0. Read only bits
D4 and D3 are revision control and the value indi-
cates the status code of the device (ie. 01 is status
code 1).
Table 4. Configuration Register 5 (D4 through D7)
Table 3. Configuration Register 5 (D0 through D3)
The delay from V
PTH0
until PUP#1 low is t
PDLY1
. There is
a similar t
PDLYX
delay for V1 to PUP#2 and for V2 to
PUP#3. They are programmed in register 7. Cascading will
always occur as indicated in the flow chart (Figure 7).
WATCHDOG TIMER
The Watchdog Timer will generate a reset if it times out. It
can be cleared by a high-to-low transition on WLDI and
restarted.
If the Watchdog times out RESET# will be driven low until
t
PRTO
at which time it will return high. Refer to Figure 4
which illustrates the action of RESET# with respect to the
Watchdog timer and the WLDI input.
If WLDI is held low the timer will free-run generating a series
of resets.
When the Watchdog times out RESET# will be generated.
When RESET# returns high (after t
PRTO
) the timer is reset
to time zero.
Register 6 is also used to set the programmable reset time-
out period (t
PRTO
) and to select the cascade option.
Cascade Delay Programming
The cascade delays are programmed in register 7. Bit 7 of
register 6 must be set to a 0 in order to enable the cascading
of the PUP# outputs. Cascading will not commence until
V
0
is above its programmed threshold.
Each PUP# (-3, -2 and -1) is delayed according to the states
of its Bit 1 and Bit 0 as indicated in Table 9. Refer to Figures
1 and 5 for the detailed timing relationship of the program-
mable power-on cascading.
Table 6. Configuration Register 6 (D0, D1, D2)
n
o
i
t
c
A
3
D
B
S
M
2
D
1
D
0
D
B
S
L
V
3
V
2
V
1
V
0
s
e
l
b
a
n
e
0
a
g
n
i
t
i
r
W
r
o
f
n
o
i
t
c
e
t
e
d
e
g
a
t
l
o
v
r
e
d
n
u
t
u
p
n
i
V
d
e
t
c
e
l
e
s
e
h
t
0
0
0
0
s
e
l
b
a
n
e
1
a
g
n
i
t
i
r
W
r
o
f
n
o
i
t
c
e
t
e
d
e
g
a
t
l
o
v
r
e
v
o
t
u
p
n
i
V
d
e
t
c
e
l
e
s
e
h
t
1
1
1
1
7
D
B
S
M
6
D
5
D
4
D
3
D
d
a
e
R
1
y
l
n
O
1
O
T
R
0
O
T
R
d
a
e
R
y
l
n
O
d
a
e
R
y
l
n
O
n
o
i
t
c
A
0
0
0
x
x
t
O
T
R
P
s
m
5
2
=
0
0
1
x
x
t
O
T
R
P
s
m
0
5
=
0
1
0
x
x
t
O
T
R
P
s
m
0
0
1
=
0
1
1
x
x
t
O
T
R
P
s
m
0
0
2
=
7
D
B
S
M
6
D
5
D
4
D
B
S
L
n
o
i
t
c
A
V
3
V
2
V
1
V
0
0
0
0
0
a
s
e
t
a
c
i
d
n
i
1
a
g
n
i
d
a
e
R
t
l
u
a
f
y
l
p
p
u
s
1
1
1
1
CONFIGURATION REGISTERS (CONTINUED)
2
D
1
D
0
D
B
S
L
n
o
i
t
c
A
2
D
W
1
D
W
0
D
W
F
F
O
0
0
0
s
m
0
0
4
0
1
1
s
m
0
0
8
1
0
0
s
m
0
0
6
1
1
0
1
s
m
0
0
2
3
1
1
0
s
m
0
0
4
6
1
1
1
12
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
SMX3200 PROGRAMMER
The end user can use the summit SMX3200 programming
cable and software that have been developed to operate
with a standard personal computer. The programming
cable interfaces directly between a PC's parallel port and
the target application. The application's values are entered
via an intuitive graphical user interface employing drop-
down menus.
The latest revisions of all software and an application brief
describing the SMX3200 is available from the website
(www.summitmicro.com).
DEVELOPMENT HARDWARE & SOFTWARE
The Windows GUI software will generate the data and send
it in I
2
C serial bus format so that it can be directly
downloaded to the SMS45 via the programming Dongle
and cable. An example of the connection interface is
shown in Figure 8.
When design prototyping is complete, the software can
generate a HEX data file that should be transmitted to
Summit for approval. Summit will then assign a unique
customer ID to the HEX code and program production
devices before the final electrical test operations. This will
ensure proper device operation in the end application.
Table 9. PUP Delays, Configuration Register 7
2047 Table09 1.0
Table 8. Configuration Register 7 (D5 through D0)
2047 Table08 3.0
Table 7. Configuration Register 7 (D7, D6)
2047 Table07 3.0
7
D
B
S
M
6
D
n
o
i
t
c
A
s
s
e
r
d
d
A
t
c
e
l
e
S
k
c
o
L
0
S
A
x
0
n
e
h
w
y
l
n
o
s
d
n
o
p
s
e
r
,
0
1
0
1
=
I
T
D
s
e
t
a
t
s
c
i
g
o
l
1
A
&
2
A
=
s
t
i
b
s
s
e
r
d
d
a
x
1
n
e
h
w
y
l
n
o
s
d
n
o
p
s
e
r
,
1
1
0
1
=
I
T
D
s
e
t
a
t
s
c
i
g
o
l
1
A
&
2
A
=
s
t
i
b
s
s
e
r
d
d
a
0
x
d
e
l
b
a
n
e
e
t
i
r
W
/
d
a
e
R
.
g
e
R
.
g
i
f
n
o
C
1
x
t
u
o
d
e
k
c
o
l
e
t
i
r
W
/
d
a
e
R
.
g
e
R
.
g
i
f
n
o
C
5
D
4
D
3
D
2
D
1
D
0
D
B
S
L
3
#
P
U
P
2
#
P
U
P
1
#
P
U
P
1
t
i
B
0
t
i
B
1
t
i
B
0
t
i
B
1
t
i
B
0
t
i
B
1
t
i
B
0
t
i
B
t
X
Y
L
D
P
0
0
y
a
l
e
D
)
o
n
(
s
m
0
0
1
y
a
l
e
D
s
m
5
2
1
0
y
a
l
e
D
s
m
0
5
1
1
y
a
l
e
D
s
m
0
0
1
1
Note 1 - Setting this bit will cause a permanent Read/Write Lock out.
CONFIGURATION REGISTERS (CONTINUED)
Pin 9, 5V
Pin 7, 10V
Pin 5, Reserved
Pin 3, GND
Pin 1, GND
Pin 6, MR#
Pin 4, SDA
Pin 2, SCL
Pin 8, Reserved
Pin 10, Reserved
Top view of straight 0.1" x 0.1 closed-side
connector. SMX3200 interface cable connector.
9
7
5
3
1
10
8
6
4
2
SMS45
SDA
SCL
VDD_CAP
GND
0.1
F
MR#
D1
C1
1N4148
Figure 8. SMX3200 Programmer I
2
C serial bus connections to program the SMS45.
13
2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Table 10. I
2
C Operating Characteristics
2047 Table10 4.0
Figure 9. I
2
C Operating Characteristics
I
2
C PROGRAMMING INFORMATION
Note (1): These values are guaranteed by design.
MEMORY OPERATION
Data for the configuration registers and the memory array
are read and written via an industry standard two-wire
interface. The bus was designed for two-way, two-line
serial communication between different integrated cir-
cuits. The two lines are a serial data line (SDA) and a
serial clock line (SCL). The SDA line must be connected
to a positive supply by a pull-up resistor, located some-
where on the bus. See Memory Operating Characteris-
tics: Table 10 and Figure 9.
Input Data Protocol
The protocol defines any device that sends data onto the
bus as a transmitter and any device that receives data as
a receiver. The device controlling data transmission is
called the Master and the controlled device is called the
Slave. In all cases the SMS45 will be a Slave device, since
it never initiates any data transfers.
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during clock high
time because changes on the data line while SCL is high
will be interpreted as start or stop condition.
tF
tR
tLOW
tHIGH
tHD:STA
tSU:STA
tBUF
tDH
tHD:DAT
tSU:DAT
tSU:STO
SCL
SDA In
SDA Out
tAA
2047 Fig09
l
o
b
m
y
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r
e
t
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m
a
r
a
P
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t
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X
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y
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C
S
0
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0
1
z
H
k
t
W
O
L
d
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p
w
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c
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C
7
.
4
s
t
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G
I
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c
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0
.
4
s
t
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)
1
(
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m
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7
.
4
s
t
A
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S
:
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p
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7
.
4
s
t
A
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S
:
D
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4
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i
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m
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A
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i
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2
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n
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i
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s
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d
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r
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t
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f
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n
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p
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1
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5
s
m
14
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Figure 10. START and STOP Conditions
2047 Table11 1.0
Table 11. Slave Addresses
START and STOP Conditions
When both the data and clock lines are high the bus is said
to be not busy. A high-to-low transition on the data line,
while the clock is high, is defined as the Start condition.
A low-to-high transition on the data line, while the clock
is high, is defined as the Stop condition. See Figure 10.
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device,
either the Master or the Slave, will release the bus after
transmitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line low to Acknowledge that it
received the eight bits of data. The Master will leave the
SDA line high (NACK) when it terminates a read function.
The SMS45 will respond with an Acknowledge after recog-
nition of a Start condition and its slave address byte. If both
the device and a write operation are selected the SMS45
will respond with an Acknowledge after the receipt of each
subsequent 8-Bit word. In the READ mode the SMS45
transmits eight bits of data, then releases the SDA line, and
monitors the line for an Acknowledge signal. If an Acknowl-
edge is detected and no Stop condition is generated by the
Master, the SMS45 will continue to transmit data. If a
NACK is detected the SMS45 will terminate further data
transmissions and await a Stop condition before returning
to the standby power mode.
Device Addressing
Following a Start condition the Master must output the
address of the Slave it is accessing. The most significant
four bits of the Slave address are the device type
identifier/address. For the SMS45 the default is 1010
BIN
.
The next two bits are the Bus Address. The next bit (the
7th) is the MSB of the memory address.
Read/Write Bit
The last bit of the data stream defines the operation to be
performed. When set to 1 a Read operation is selected;
when set to 0 a Write operation is selected.
WRITE OPERATIONS
The SMS45 allows two types of Write operations: byte
Write and page Write. A byte Write operation writes a
single byte during the nonvolatile write period (t
WR
). The
page Write operation, limited to the memory array, allows
up to 16 bytes in the same page to be written during t
WR
.
Byte Write
After the Slave address is sent (to identify the Slave
device and select either a Read or Write operation), a
second byte is transmitted which contains the low order
8 bit address of any one of the 512 words in the array.
Upon receipt of the word address the SMS45 responds with
an Acknowledge. After receiving the next byte of data it
again responds with an Acknowledge. The Master then
terminates the transfer by generating a Stop condition, at
which time the SMS45 begins the internal Write cycle.
While the internal Write cycle is in progress the SMS45
inputs are disabled and the device will not respond to any
requests from the Master.
Page Write (memory only)
The SMS45 is capable of a 16-byte page Write operation.
It is initiated in the same manner as the byte Write
operation, but instead of terminating the Write cycle after
the first data word the Master can transmit up to 15 more
bytes of data. After the receipt of each byte the SMS45 will
respond with an Acknowledge.
The SMS45 automatically increments the address for
subsequent data words. After the receipt of each word the
low order address bits are internally incremented by one.
2047 Fig10
SCL
SDA In
START
Condition
STOP
Condition
7
D
B
S
M
6
D
5
D
4
D
3
D
2
D
1
D
0
D
B
S
L
s
t
i
B
s
s
e
r
d
d
A
e
p
y
T
e
c
i
v
e
D
s
u
B
B
S
M
W
/
R
5
4
S
M
S
x
x
x
x
1
0
0
1
r
e
t
s
i
g
e
R
n
o
i
t
a
r
u
g
i
f
n
o
C
1
0
1
0
)
t
l
u
a
f
e
d
(
y
r
o
m
e
M
1
0
1
1
y
r
o
m
e
M
e
t
a
n
r
e
t
l
A
I
2
C PROGRAMMING INFORMATION (CONTINUED)
15
2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Figure 11. Read and Write Operations
The high order bits of the address byte remain constant.
Should the Master transmit more than 16 bytes, prior to
generating the Stop condition, the address counter will
rollover and the previously written data will be overwrit-
ten. As with the byte Write operation, all inputs are disabled
during the internal Write cycle. Refer to Figure 11 for the
address, Acknowledge, and data transfer sequence.
N
A
C
K
N
A
C
K
Typical Write Operation
(Standard memory device type)
S
T
A
R
T
A
C
K
B
A
2
B
A
1
A
8
R
/
W
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
S
T
O
P
Master
SDA
Slave
0
1
1 0
A
C
K
R
/
W
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
S
T
O
P
S
T
A
R
T
Writing Configuration Registers
Master
SDA
Slave
0 1
1 0
Master
SDA
Slave
Device Type
Address
Bus
Address
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
R
/
W
A
C
K
S
T
A
R
T
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
Reading the Configuration Register
0 1
1 0
A
C
K
R
/
W
S
T
O
P
S
T
A
R
T
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0 1
1 0
Up to 15
additional bytes
can be written
before issuing
the stop.
B
A
2
B
A
1
X
B
A
2
B
A
1
X
B
A
2
B
A
1
X
2047 Fig11
Typical Reading Operation
(Alternate memory device type)
Master
SDA
Slave
A
C
K
R
/
W
A
C
K
S
T
A
R
T
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1 1
1 0
A
C
K
R
/
W
S
T
O
P
S
T
A
R
T
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 1
1 0
B
A
2
B
A
1
A
8
B
A
2
B
A
1
A
8
I
2
C PROGRAMMING INFORMATION (CONTINUED)
16
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Figure 12. Write Flow Chart
Acknowledge Polling
When the SMS45 is performing an internal Write operation
it will ignore any new Start conditions. Since the device will
only return an acknowledge after it accepts the Start the
part can be continuously queried until an acknowledge is
issued, indicating that the internal Write cycle is complete.
See the flow chart for the proper sequence of operations for
polling.
READ OPERATIONS
Read operations are initiated with the R/W bit of the
identification field set to 1. There are two different Read
options: 1. Current Address Byte Read, and 2. Random
Address Byte Read.
Current Address Read (memory only)
The SMS45 contains an internal address counter which
maintains the address of the last word accessed, incre-
mented by one. If the last address accessed (either a
Read or Write) was to address location n, the next Read
operation would access data from address location n+1
and increment the current address pointer. When the
SMS45 receives the Slave address field with the R/W bit
set to 1 it issues an acknowledge and transmits the 8-Bit
word stored at address location n+1. The current address
byte Read operation only accesses a single byte of data.
The Master sets the SDA line to NACK and generates a
stop condition. At this point the SMS45 discontinues data
transmission.
Random Address Read (Register and Memory)
Random address Read operations allow the Master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the Master
issues a write command which includes the start condi-
tion and the Slave address field (with the R/W bit set to
Write), followed by the address of the word it is to Read.
This procedure sets the internal address counter of the
SMS45 to the desired address. After the word address
acknowledge is received by the Master it immediately
reissues a Start condition, followed by another Slave
address field with the R/W bit set to READ. The SMS45 will
respond with an Acknowledge and then transmit the 8 data
bits stored at the addressed location. At this point the
Master sets the SDA line to NACK and generates a Stop
condition. The SMS45 discontinues data transmission and
reverts to its standby power mode.
Sequential READ (Memory Only)
Sequential Reads can be initiated as either a current
address Read or random access Read. The first word is
transmitted as with the other byte Read modes (current
address byte Read or random address byte Read);
however, the Master now responds with an Acknowledge,
indicating that it requires additional data from the SMS45.
The SMS45 continues to output data for each Acknowl-
edge received. The Master terminates the sequential
Read operation by responding with a NACK, and issues
a Stop condition. During a sequential Read operation the
internal address counter is automatically incremented
with each Acknowledge signal. For Read operations all
address bits are incremented, allowing the entire array to
be read using a single Read command. After a count of
the last memory address the address counter will rollover
and the memory will continue to output data.
Next
Operation
a Write?
ACK
Returned
Issue
Address
Proceed
With
Write
Await
Next
Command
Issue Stop
Issue Slave
Address and
R/W = 0
Issue Stop
Write Cycle
In Progress
Yes
No
Issue Start
2047 Fig12
Yes
No
I
2
C PROGRAMMING INFORMATION (CONTINUED)
17
2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
Figure 13. Typical applications schematic, the SMX3200 programmer has internal SDA and SCL pullup
resistors.
APPLICATIONS
U1
SM S45
1
2
3
4
5
6 7
8
9 10
11
12
13
14
15
16
MR
#
V1
V2
PUP#1
PUP#2
A1 A2
GN
D
SD
A
SC
L
R
ESE
T
#
V
D
D_
CA
P
PUP#3
V3
WL
D
I
V0
C2
0.01uF
V3
PUP#2
VDD_CAP
R2
10K
D6
DIODE
C5
0.1uF
PUP#1
VDD_CAP
MR#
J1
I2C SMX3200
1
2
3
4
5
6
7
8
9
10
Gnd
SCL
Gnd3
SDA
Rsrv 5
MR#
+10V
Rsrv 8
+5V
Rsrv 10
WLDI
C3
0.01uF
PUP#3
C1
0.01uF
V2
R4
10K
C4
0.01uF
RESET#
R1
10K
V0
V1
VDD_CAP
VDD_CAP
R3
10K
18
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
DEFAULT CONFIGURATION REGISTER SETTINGS - SMS45GC-230
R egister C ontents
Function
R 00
56
V0 threshold set to 3.090V
R 01 28
V1 threshold set to 2.400V
R 02 A 0
V2 threshold set to 1.400V
R 03 14
V3 threshold set to 0.700V
R 04 F3
R eset Trigger source set for all channels, V0, V1 set to high range and V2, V3
set to low range
R 05 X 0
U pper bits are volatile status indication of input supply condition. V 0, V 1, V 2
and V 3 set to m onitor U V U nder V oltage.
R 06 4D
R eset tim eout set to 100m s, W atchdog Tim er set to 1.6s. Bits D 4 and D 3
indicate revision control.
R 07 6A
EE m em ory slave address is 1011, configuration registers are unlocked,
cascading delays are all 50m s
The default device ordering number is SMS45GC-230, is programmed as described above and tested
over the commercial temperature range.
19
2079 1.2 05/24/04
SMS45
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
PACKAGE
16 PIN SSOP PACKAGE
0.007 - 0.010
(0.18 - 0.25)
0.150 - 0.157
(3.81 - 3.99)
0.025
(0.635)
0.016 - 0.050
(0.41 - 1.27)
0.008 - 0.012
(0.20 - 0.31)
0.189 - 0.197
(4.80 - 5.00)
0.228 - 0.244
(5.79 - 6.20)
Pin 1
0.004 - 0.010
(0.10 - 0.25)
0.059
(1.50)
0.053 - 0.069
(1.35 - 1.75)
MAX
16 Pin SSOP
Ref. JEDEC MO-137
Inches
(Millimeters)
0" Min to
8" Max
20
SMS45
2079 1.2 05/24/04
SUMMIT MICROELECTRONICS, Inc.
Preliminary Information
ORDERING INFORMATION
NOTICE
NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited
characterization.
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design,
performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license
under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained
herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this
publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or
malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness.
Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction,
that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics,
Inc. is adequately protected under the circumstances.
Revision 1.2 - This document supersedes all previous versions. Please check the Summit Microelectronics, Inc. web site at
www.summitmicro.com
for data sheet updates.
Copyright 2004 SUMMIT MICROELECTRONICS, Inc.
PROGRAMMABLE ANALOG FOR A DIGITAL WORLDTM
I2C is a trademark of Philips Corporation.
S M S 4 5
G
n n n
P a c k a g e
G = 1 6 L e a d S S O P
P a r t N u m b e r S u f f i x ( s e e p a g e 1 8 )
S u m m i t P a r t
N u m b e r
S p e c if ic r e q u ir e m e n t s a r e c o n t a in e d in t h e
s u f f ix s u c h a s H e x c o d e , H e x c o d e r e v is io n , e t c .
C
T e m p R a n g e
C = C o m m e r c ia l
B la n k = I n d u s t r ia l
SMS45G
AYYWW
Pin 1
Identifier
Annn
Summit Part Number
Date Code (YYWW)
Part Number suffix
(Contains Customer specific ordering requirements)
Lot tracking code (Summit use)
Drawing not to scale
xx
Status Tracking Code
(Blank, MS, ES, 01, 02,...)
(Summit Use)
Product Tracking Code (Summit use)
SUMMIT
PART MARKING
PDF 
ZIP