1
HV257
A122104
32-Channel High Voltage
Sample and Hold Amplifier Array
Features
32 independent high voltage amplifiers
300V operating voltage
295V output voltage
2.2V/s typical output slew rate
Adjustable output current source limit
Adjustable output current sink limit
Internal closed loop gain of 72V/V
12M feedback impedance
Layout ideal for die applications
Application
MEMS (microelectromechanical systems) driver
Piezoelectric transducer driver
Optical crosspoint switches (using MEMS technology)
General Description
The Supertex HV257 is a 32-channel high voltage sample and
hold amplifier array integrated circuit. It operates on a single high
voltage supply, up to 300V, and two low voltage supplies, V
DD
and V
NN
.
All 32 sample and hold circuits share a common analog input,
Vsig. The individual sample and hold circuits are selected by a
5 to 32 logic decoder. The sampled voltage on the holding
capacitor is buffered by a low voltage amplifier and amplified by
a high voltage amplifier with a closed loop gain of 72V/V. The
internal closed loop gain is set for an input voltage range of 0V
to 4.096V. The input voltage can be up to 5.0V, but the output will
saturate. The maximum output voltage swing is 5V below the V
PP
high voltage supply. The outputs can drive capacitive loads of up
to 3000pF.
The maximum output source and sink current can be adjusted by
using two external resistors. An external R
SOURCE
resistor
controls the maximum sourcing current and an external R
SINK
resistor controls the maximum sinking current. The current limit
is approximately 12.5V divided by the external resistor value.
The setting is common for all 32 outputs. A low voltage silicon
junction diode is made available to help monitor the die
temperature.
Demo Kit
Available
HV257
V
SIG
A
0
EN
A
3
A
2
A
4
HV
OUT
0
Supertex HV257
High Voltage
Power Supply
Low Voltage
Power Supply
32
DGND
AGND
HV
OUT
1
MEMS
Array
y
y
x
x
HV
OUT
2
HV
OUT
3
HV
OUT
30
HV
OUT
31
A
1
V
NN
Low Voltage
Channel
Select
Sample
and Hold
High Voltage
OpAmp Array
R
SOURCE
R
SINK
Micro
Processor
DAC
A122104
Typical Application
2
HV257
A122104
V
P
P
High voltage positive supply
125
300
V
D
D
Low voltage positive supply
6.0
7.5
V
N
N
Low voltage negative supply
-4.5
-6.5
I
P
P
V
P
P
supply current
0.8
mA
I
D
D
V
D
D
supply current
4.3
mA
I
N
N
V
N
N
supply current
-5.2
mA
T
J
Junction temperature range
-10
125
C
V
H
T
U
O
V
H
T
U
O
voltage swing
V
PP
-5
V
S
O
N
I
Input voltage offset
50
mV
d.
e
r
r
e
f
e
r
t
u
p
n
I
R
S
V
H
T
U
O
slew rate rise
2.2
V/
s
ad
o
L
o
N
V
H
T
U
O
slew rate fall
2.0
V/
s
ad
o
L
o
N
BW
HV
T
U
O
-3dB channel bandwidth
4.0
KHz
A
O
Open loop gain
70
100
dB
A
V
Closed loop gain
68.4
72.0
75.6
V/V
R
B
F
V
H
Feedback resistance from
T
U
O
to ground
9.6
12
M
C
D
A
O
L
V
H
T
U
O
capacitive load
3000
pF
I
E
C
R
U
O
S
V
H
T
U
O
sourcing current limiting range
385
550
715
A
R
E
C
R
U
O
S
K
5
2
=
I
K
N
I
S
V
H
T
U
O
sinking current limiting range
385
550
715
A
R
K
N
I
S
K
5
2
=
R
E
C
R
U
O
S
External resistance range for setting current
source limit
25
250
K
R
K
N
I
S
External resistance range for setting current
sink limit
25
250
K
T
C
C
D
DC channel to channel crosstalk
-80
dB
R
R
S
P
V
Power supply rejection ratio for
P
P
V
,
D
D
V
d
n
a
,
N
N
-40
dB
V
V
V
V
PP
= 300V, All HV
OUT
= 0V, No Load
V
NN
= -4.5V to -6.5V
V
DD
= 6.0V to 7.5V
0
V
V
PP
= 300V
0
Ordering Information
e
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P
HV257
295V
72V/V
HV257FG
HV257X
100Lead MQFP
Die
Absolute Maximum Ratings*
V
PP
, High voltage supply
310V
AV
DD
, Analog low voltage positive supply
8.0V
DV
DD
, Digital low voltage positive supply
8.0V
AV
NN
, Analog low voltage negative supply
-7.0V
DV
NN
, Digital low voltage negative supply
-7.0V
Logic input voltage
-0.5V to DV
DD
V
IN
, Analog input signal
0V to 6.0V
Storage temperature range
-65C to 150C
Maximum junction temperature
150C
*Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device
at the absolute rating level may affect device reliability. All voltages are referenced to device
ground.
Electrical Characteristics
(Over operating conditions unless otherwise noted.)
Symbol
Parameters
Min
Typ
Max
Unit
Condition
High Voltage Amplifier
Operating Conditions
3
HV257
A122104
Symbol
Parameter
Min
Typ
Max
Units
Conditions
Symbol
Min
Typ
Max
Units
Conditions
V
PED
Pedestal Voltage
mV
R
SW
Sample and Hold Switch resistance
5.0
K
C
Sample and Hold Capacitor
10
pF
RD
ROOP
Droop rate during hold time relative to input
2.0
V/s
V
SIG
Input voltage range
5.0
T
SU
Set-up time-address to enable
75
ns
T
H
Hold time-address to enable bar
75
ns
V
IH
Input logic high voltage
2.4
D
D
V
V
IL
Input logic low voltage
1.2
l
IH
Input logic high current
1.0
A
=
V
IH
D
D
l
IL
Input logic low current
-1.0
A
0
=
V
IL
PIV
Peak inverse voltage
5.0
cathode to anode
V
F
Forward diode drop
If = 100
A, anode to cathode@25
O
C
I
F
Forward diode current
100
A
anode to cathode
T
C
V
F
temperature coefficient
-2.20
C
/
V
m
anode to cathode
0
V
Parameter
Symbol
Min
Typ
Max
Units
Conditions
Parameter
V
V
V
V
0
V
V
1.0
12.0
input referred
output referred
0.60
Acceptable Power Up Sequences
1) V
PP
2) V
NN
3) V
DD
4) Inputs & Anode
or
1) V
NN
2) V
DD
3) V
PP
4) Inputs & Anode
Acceptable Power Down Sequences
1) Inputs & Anode
2) V
DD
3) V
NN
4) V
PP
or
1) Inputs & Anode
2) V
PP
3) V
DD
4) V
NN
Power Up/Down Sequence
The device can be damaged due to improper power up / down
sequence. To prevent damage, please follow the acceptable
power up /down sequences and add two external diodes as
shown in the diagram below. The first diode is a high voltage
diode across V
PP
and V
DD
where the anode of the diode is
connected to V
DD
and the cathode of the diode is connected to
Vpp. Any low current high voltage diode such as a 1N4004 will
be adequate. The second diode is a schottky diode across V
NN
and DGnd where the anode of the schottky diode is connected
to V
NN
and the cathode is connected to DGnd. Any low current
schottky diode such as a 1N5817 will be adequate.
V
DD
V
PP
1N4004
or similar
V
NN
DGND
1N5817
or similar
Sample and Hold
Logic Decoder
Diode
4
HV257
A122104
Block Diagram
71R
R
AV
NN
HV
OUT
0
V
PP
AV
NN
AV
DD
S/H - 0
5 to 32
Decoder
V
SIG
A0
A1
A2
A3
EN
A4
71R
R
S/H - 1
HV
OUT
1
V
PP
71R
R
S/H - 31
HV
OUT
31
V
PP
AV
DD
AV
NN
AV
NN
C
H
-
+
-
+
Q0
Q1
Q31
HV
OUT
Current
Sink
Limiting
To all HV
OUT
amplifiers
To all HV
OUT
amplifiers
R
SOURCE
R
SINK
DV
DD
AV
NN
DGND
To internal digital V
DD
bus
To internal analog V
NN
bus
AGND
V
PP
AV
DD
To internal V
PP
bus
To internal analog V
DD
bus
DV
DD
DV
NN
To internal digital V
NN
bus
AV
DD
AV
NN
AV
NN
C
H
C
H
Byp-V
PP
Byp-AV
DD
Byp-AV
NN
Anode
Cathode
Bias Circuit
-
+
-
+
-
+
-
+
HV
OUT
Current
Source
Limiting
5
HV257
A122104
4
A
3
A
2
A
1
A
0
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2
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1
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Pin Description
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