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Электронный компонент: HV507X

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1
HV507
Features
HVCMOS
technology
Operating output voltage of 300V
Low power level shifting from 5V to 300V
Shift register speed 8MHz @ V
DD
= 5V
64 latched data outputs
Output polarity and blanking
CMOS compatible inputs
Forward and reverse shifting options
300V, 64-Channel Serial to Parallel Converter
with High Voltage Push-Pull Outputs
12/13/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
Absolute Maximum Ratings
1
Supply voltage, V
DD
-0.5V to +6V
Supply voltage, V
PP
V
DD
to 320V
Logic input levels
-0.5V to V
DD
+0.5V
Ground current
3
0.5A
High voltage supply current
2
0.5A
Continuous total power dissipation
3
1200mW
Operating temperature range
0C to +70C
Storage temperature range
-65C to +150C
Notes:
1. All voltages are referenced to GND.
2. Connection to all power and ground pads is required. Duty cycle is limited by
the total power dissipated in the package.
3. For operation above 25C ambient derate linearly to 70C at 26.7mW/C.
General Description
The HV507 is a low voltage serial to high voltage parallel con-
verter with 64 high voltage push-pull outputs. This device has
been designed for use as a printer driver for electrostatic applica-
tions. It can also be used in any application requiring multiple high
voltage outputs, low current sourcing and sinking capabilities.
The device consists of a 64-bit shift register, 64 latches, and
control logic to perform the polarity select and blanking of the
outputs. A DIR pin controls the direction of data shift through the
device. With DIR grounded, D
IOA
is Data In and D
IOB
is Data Out;
data is shifted from HV
OUT
64 to HV
OUT
1. When DIR is at logic high,
D
IOB
is Data In and D
IOA
is Data Out: data is then shifted from
HV
OUT
1 to HV
OUT
64. Data is shifted through the shift register on
the low to high transition of the clock. Data output buffers are
provided for cascading devices. Operation of the shift register is
not affected by the LE, BL, or the POL inputs. Transfer of data from
the shift register to the latch occurs when the LE is high. The data
in the latch is stored during LE transition from high to low.
Ordering Information
Package Options
Recommended Operating
80-Lead Plastic
Device
V
PP
Max*
Gullwing
Die
HV507
300V
HV507PG
HV507X
* Please consult factory for higher voltage operation.
2
HV507
Symbol
Parameter
Min
Typ
Max
Units
Conditions
f
CLK
Clock frequency
8
MHz
t
W
Clock width high and low
62
ns
t
SU
Data setup time before clock rises
35
ns
t
H
Data hold time after clock rises
30
ns
t
WLE
Width of latch enable pulse
80
ns
t
DLE
LE delay time after rising edge of clock
35
ns
t
SLE
LE setup time before rising edge of clock
40
ns
t
ON
, t
OFF
Time from latch enable to HV
OUT
4
s
C
L
= 20pF
t
DHL
Delay time clock to data out high to low
125
ns
C
L
= 20pF
t
DLH
Delay time clock to data out low to high
125
ns
C
L
= 20pF
t
r
, t
f
All logic inputs
5
ns
Note:
1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec.
Symbol
Parameter
Min
Typ
Max
Units
Conditions
I
DD
V
DD
supply current
15
mA
f
CLK
= 8MHz, f
DATA
= 4MHz
LE = LOW
I
DDQ
Quiescent V
DD
supply current
200
A
All V
IN
= 0V or V
DD
I
PP
High voltage supply current
0.50
mA
V
PP
= 300V All outputs high
0.50
mA
V
PP
= 300V All outputs low
I
IH
High-level logic input current
10
A
V
IH
= V
DD
I
IL
Low-level logic input current
-10
A
V
IL
= 0V
V
OH
High-level output
HV
OUT
265
V
V
PP
= 300V, IHV
OUT
= -1mA
Data out
V
DD
-1V
V
ID
OUT
= -100A
V
OL
Low-level output
HV
OUT
35
V
V
DD
= 5V, IHV
OUT
= 1mA
Data out
1.0
V
ID
OUT
= 100A
V
OC
HV
OUT
clamp voltage
V
PP
+1.5
V
I
OC
= 1mA
-30
V
I
OC
= -1mA
Symbol
Parameter
Min
Typ
Max
Units
V
DD
Logic supply voltage
4.5
5.0
5.5
V
V
PP
High voltage supply
60
300
V
V
IH
High-level input voltage
V
DD
-0.9
V
DD
V
V
IL
Low-level input voltage
0
0.9
V
T
A
Operating free-air temperature
0
+70
C
Notes:
Power-up sequence should be the following:
1. Connect ground.
4. Apply V
PP
.
2. Apply V
DD
.
5. The V
PP
should not drop below V
DD
or float during operation.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
Power-down sequence should be the reverse of the above.
Electrical Characteristics
(for V
DD
= 5V, V
PP
= 300V, T
A
= 25
0
C)
DC Characteristics
Recommended Operating Conditions
AC Characteristics
1
(For V
DD
= 5V, V
PP
= 300V, T
A
= 25C)
3
HV507
LE
HV
OUT
w/ S/R LOW
Data Valid
50%
50%
Data In
(D
IOA
/D
IOB
)
CLK
50%
50%
50%
t
SU
t
H
t
WL
t
WH
50%
50%
t
DLH
t
DHL
50%
t
WLE
t
DLE
t
SLE
50%
50%
t
ON
10%
HV
OUT
w/ S/R HIGH
90%
90%
10%
t
OFF
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
V
IH
V
OL
V
OH
V
OL
V
OH
V
OL
Data Out
(D
IOA
/D
IOB
)
V
DD
Input
GND
V
PP
HVGND
HV
OUT
Logic Inputs
GND
Data Out
Logic Data Output
High Voltage Outputs
V
DD
Input and Output Equivalent Circuits
Switching Waveforms
4
HV507
HV
OUT
2


60 Additional
Outputs


POL
BL
LE
CLK
64-bit
Static Shift
Register
64 Latches
HV
OUT
63
V
PP
HV
OUT
1
DIR
D
IOA
D
IOB
HV
OUT
64
L/T
L/T
L/T
L/T
Functional Block Diagram
Inputs
Outputs
Function
Shift Reg
HV Outputs
Data Out
1
2...64
1
2...64
*
All on
X
X
X
L
L
X
*
*...*
H
H...H
*
All off
X
X
X
L
H
X
*
*...*
L
L...L
*
Invert mode
X
X
L
H
L
X
*
*...*
*
*...*
*
Load S/R
H or L
L
H
H
X
H or L *...*
*
*...*
*
Store data
X
X
H
H
X
*
*...*
*
*...*
*
in latches
X
X
H
L
X
*
*...*
*
*...*
*
Transparent
L
H
H
H
X
L
*...*
L
*...*
*
latch mode
H
H
H
H
X
H
*...*
H
*...*
*
D
IOA
X
X
X
L
Q
n
Q
n-1
--
D
IOB
D
IOB
X
X
X
H
Q
n
Q
n+1
--
D
IOA
Notes:
H = high level, L = low level, X = irrelevant, = low-to-high transition, = high-to-low transition.
* = dependent on previous stage's state before the last CLK or last LE high.
Data
CLK
LE
BL
POL
DIR
I/O relation
Function Table
L/T = Level Translator
5
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
12/13/010
2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
HV507
Pin
Function
Pin
Function
1
HV
OUT
41
41
HV
OUT
1
2
HV
OUT
42
42
HV
OUT
2
3
HV
OUT
43
43
HV
OUT
3
4
HV
OUT
44
44
HV
OUT
4
5
HV
OUT
45
45
HV
OUT
5
6
HV
OUT
46
46
HV
OUT
6
7
HV
OUT
47
47
HV
OUT
7
8
HV
OUT
48
48
HV
OUT
8
9
HV
OUT
49
49
HV
OUT
9
10
HV
OUT
50
50
HV
OUT
10
11
HV
OUT
51
51
HV
OUT
11
12
HV
OUT
52
52
HV
OUT
12
13
HV
OUT
53
53
HV
OUT
13
14
HV
OUT
54
54
HV
OUT
14
15
HV
OUT
55
55
HV
OUT
15
16
HV
OUT
56
56
HV
OUT
16
17
HV
OUT
57
57
HV
OUT
17
18
HV
OUT
58
58
HV
OUT
18
19
HV
OUT
59
59
HV
OUT
19
20
HV
OUT
60
60
HV
OUT
20
21
HV
OUT
61
61
HV
OUT
21
22
HV
OUT
62
62
HV
OUT
22
23
HV
OUT
63
63
HV
OUT
23
24
HV
OUT
64
64
HV
OUT
24
25
V
PP
65
HV
OUT
25
26
D
IOA
66
HV
OUT
26
27
N/C
67
HV
OUT
27
28
N/C
68
HV
OUT
28
29
BL
69
HV
OUT
29
30
POL
70
HV
OUT
30
31
V
DD
71
HV
OUT
31
32
DIR
72
HV
OUT
32
33
GND
73
HV
OUT
33
34
HVGND
74
HV
OUT
34
35
N/C
75
HV
OUT
35
36
N/C
76
HV
OUT
36
37
CLK
77
HV
OUT
37
38
LE
78
HV
OUT
38
39
D
IOB
79
HV
OUT
39
40
V
PP
80
HV
OUT
40
Pin Configurations
Package Outline
65
80
1
24
25
40
41
64
Index
top view
80-pin Gullwing Package
HV507
80 Pin Gullwing Package