1
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
TN5325
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
BV
DSS
/
R
DS(ON)
V
GS(th)
I
D(on)
BV
DGS
(max)
(max)
(min)
TO-236AB*
TO-92
TO-243AA**
250V
7.0
2.0V
1.2A
TN5325K1
TN5325N3
TN5325N8
* Same as SOT-23. All units shipped on 3,000 piece carrier tape reels.
** Shipped on 2,000 piece carrier tape and reels.
Order Number / Package
Product marking for SOT-23:
N3C
where
= 2-week alpha date code
Ordering Information
Absolute Maximum Ratings
Drain-to-Source Voltage
BV
DSS
Drain-to-Gate Voltage
BV
DGS
Gate-to-Source Voltage
20V
Operating and Storage Temperature
-55
C to +150
C
Soldering Temperature*
300
C
*
Distance of 1.6 mm from case for 10 seconds.
Features
Low threshold 2.0V max.
Free from secondary breakdown
Low power drive requirement
Low C
ISS
and fast switching speeds
Excellent thermal stability
High input impedance and high gain
Complementary N- and P-channel devices
Applications
Logic level interfaces ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Advanced DMOS Technology
These enhancement-mode (normally-off) transistors utilize a
vertical DMOS structure and Supertex's well-proven silicon-gate
manufacturing process. This combination produces devices with
the power handling capabilities of bipolar transistors and with the
high input impedance and positive temperature coefficient inher-
ent in MOS devices. Characteristic of all MOS structures, these
devices are free from thermal runaway and thermally-induced
secondary breakdown.
Supertex's vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where high breakdown
voltage, high input impedance, low input capacitance, and fast
switching speeds are desired.
Note: See Package Outline section for dimensions.
Package Options
S G D
TO-92
TO-243AA
(SOT-89)
G
D
S
D
TO-236AB
(SOT-23)
G
S
D
Product marking for TO-243AA
Where
= 2-week alpha date code
TN3C
2
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 FAX: (408) 222-4895
www.supertex.com
11/12/01
2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
Package
I
D
(continuous)*
I
D
(pulsed)
Power Dissipation
jc
ja
I
DR
*
I
DRM
@ T
A
= 25
C
C/W
C/W
TO-236AB
150mA
400mA
0.36W
200
350
150mA
400mA
TO-92
215mA
800mA
0.74W
125
170
215mA
800mA
TO-243AA
316mA
1.5A
1.6W**
15
78**
316mA
1.5A
*
I
D
(continuous) is limited by max rated T
j
.
**Mounted on FR5 board. 25mm x 25mm x 1.57mm. Significant PD increase possible on ceramic substrate.
Thermal Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
BV
DSS
Drain-to-Source Breakdown Voltage
250
V
I
D
= 100
A, V
GS
= 0V
V
GS(th)
Gate Threshold Voltage
0.6
2.0
V
V
GS
= V
DS
, I
D
= 1mA
V
GS(th)
Change in V
GS(th)
with Temperature
-4.5
mV/
C
I
D
= 1mA, V
GS
= V
DS
I
GSS
Gate Body Leakage
100
nA
V
GS
=
20V, V
DS
= 0V
I
DSS
Zero Gate Voltage Drain Current
1.0
A
V
GS
= 0V, V
DS
= 100V
10.0
A
V
GS
= 0V, V
DS
= Max Rating
1.0
mA
V
GS
= 0V, V
DS
= 0.8 Max Rating
T
A
= 125
C
I
D(ON)
ON-State Drain Current
0.6
A
V
GS
= 4.5V, V
DS
= 25V
1.2
V
GS
= 10V, V
DS
= 25V
R
DS(ON)
Static Drain-to-Source
8.0
V
GS
= 4.5V, I
D
= 150mA
ON-State Resistance
7.0
V
GS
= 10V, I
D
= 1.0A
R
DS(ON)
Change in R
DS(ON)
with Temperature
1.0
%/
C
V
GS
= 4.5V, I
D
= 150mA
G
FS
Forward Transconductance
150
m
V
DS
= 25V, I
D
= 200mA
C
ISS
Input Capacitance
110
C
OSS
Common Source Output Capacitance
60
pF
V
GS
= 0V, V
DS
= 25V, f = 1MHz
C
RSS
Reverse Transfer Capacitance
23
t
d(ON)
Turn-ON Delay Time
20
t
r
Rise Time
15
t
d(OFF)
Turn-OFF Delay Time
25
t
f
Fall Time
25
V
SD
Diode Forward Voltage Drop
1.8
V
I
SD
= 200mA, V
GS
= 0V
t
rr
Reverse Recovery Time
300
ns
I
SD
= 200mA, V
GS
= 0V
Notes:
1.All D.C. parameters 100% tested at 25
C unless otherwise stated. (Pulse test: 300
s pulse, 2% duty cycle.)
2.All A.C. parameters sample tested.
Electrical Characteristics
(@ 25
C unless otherwise specified)
V
DD
= 25V
ns
I
D
= 150mA
R
GEN
= 25
Switching Waveforms and Test Circuit
90%
10%
90%
90%
10%
10%
PULSE
GENERATOR
V
DD
R
L
OUTPUT
D.U.T.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
F
t
r
INPUT
INPUT
OUTPUT
10V
V
DD
R
gen
0V
0V
TN5325
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